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Autoroute mux12 board

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This commit is contained in:
Klemens Schölhorn 2018-03-08 23:56:45 +01:00
parent a5cb833b1d
commit 7cbc757b1a
3 changed files with 789 additions and 162 deletions
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64
boards/mux12/mux12-cache.lib
View File

@ -6,8 +6,8 @@ EESchema-LIBRARY Version 2.3
DEF 74LS257 U 0 10 Y Y 1 F N
F0 "U" 50 150 50 H V C CNN
F1 "74LS257" 50 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
X GND 8 -350 -600 0 U 50 50 0 0 W N
X VCC 16 -350 600 0 U 50 50 0 0 W N
@ -29,31 +29,27 @@ X OE 15 -750 -550 300 R 50 50 1 1 I I
ENDDRAW
ENDDEF
#
# Conn_01x04
# CONN_01X03
#
DEF Conn_01x04 J 0 40 Y N 1 F N
F0 "J" 0 200 50 H V C CNN
F1 "Conn_01x04" 0 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DEF CONN_01X03 P 0 40 Y N 1 F N
F0 "P" 0 200 50 H V C CNN
F1 "CONN_01X03" 100 0 50 V V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Connector*:*_??x*mm*
Connector*:*1x??x*mm*
Pin?Header?Straight?1X*
Pin?Header?Angled?1X*
Socket?Strip?Straight?1X*
Socket?Strip?Angled?1X*
Pin_Header_Straight_1X03
Pin_Header_Angled_1X03
Socket_Strip_Straight_1X03
Socket_Strip_Angled_1X03
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 150 50 -250 1 1 10 f
X Pin_1 1 -200 100 150 R 50 50 1 1 P
X Pin_2 2 -200 0 150 R 50 50 1 1 P
X Pin_3 3 -200 -100 150 R 50 50 1 1 P
X Pin_4 4 -200 -200 150 R 50 50 1 1 P
S -50 -95 10 -105 0 1 0 N
S -50 5 10 -5 0 1 0 N
S -50 105 10 95 0 1 0 N
S -50 150 50 -150 0 1 0 N
X P1 1 -200 100 150 R 50 50 1 1 P
X P2 2 -200 0 150 R 50 50 1 1 P
X P3 3 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
@ -106,10 +102,10 @@ ENDDEF
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
@ -117,13 +113,13 @@ ENDDEF
# PWR_FLAG
#
DEF PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 75 50 H I C CNN
F1 "PWR_FLAG" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
F0 "#FLG" 0 95 50 H I C CNN
F1 "PWR_FLAG" 0 180 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
X pwr 1 0 0 0 U 50 50 0 0 w
P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
ENDDRAW
ENDDEF
#
@ -132,11 +128,11 @@ ENDDEF
DEF VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
P 2 0 1 0 0 0 0 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF

843
boards/mux12/mux12.kicad_pcb
View File

@ -1,15 +1,15 @@
(kicad_pcb (version 4) (host pcbnew 4.0.7)
(kicad_pcb (version 4) (host pcbnew 4.0.2+dfsg1-stable)
(general
(links 48)
(no_connects 48)
(area 137.492381 67.815 164.76762 135.485)
(no_connects 0)
(area 137.16 67.565 165.228334 138.255)
(thickness 1.6)
(drawings 0)
(tracks 0)
(tracks 380)
(zones 0)
(modules 7)
(nets 41)
(nets 40)
)
(page A4)
@ -37,15 +37,15 @@
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(last_trace_width 0.2)
(trace_clearance 0.3)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_size 0.8)
(via_drill 0.5)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
@ -64,7 +64,7 @@
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x00030_80000001)
(layerselection 0x00000_80000001)
(usegerberextensions false)
(excludeedgelayer true)
(linewidth 0.100000)
@ -83,8 +83,8 @@
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(outputformat 4)
(mirror true)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
@ -116,32 +116,30 @@
(net 23 "Net-(J2-Pad11)")
(net 24 "Net-(J2-Pad12)")
(net 25 /SEL)
(net 26 /~OE)
(net 27 VCC)
(net 28 GND)
(net 29 "Net-(J4-Pad1)")
(net 30 "Net-(J4-Pad2)")
(net 31 "Net-(J4-Pad3)")
(net 32 "Net-(J4-Pad4)")
(net 33 "Net-(J4-Pad5)")
(net 34 "Net-(J4-Pad6)")
(net 35 /Absicht_BITCH)
(net 36 "Net-(J4-Pad8)")
(net 37 "Net-(J4-Pad9)")
(net 38 "Net-(J4-Pad10)")
(net 39 "Net-(J4-Pad11)")
(net 40 "Net-(J4-Pad12)")
(net 26 VCC)
(net 27 GND)
(net 28 "Net-(J4-Pad1)")
(net 29 "Net-(J4-Pad2)")
(net 30 "Net-(J4-Pad3)")
(net 31 "Net-(J4-Pad4)")
(net 32 "Net-(J4-Pad5)")
(net 33 "Net-(J4-Pad6)")
(net 34 /Absicht_BITCH)
(net 35 "Net-(J4-Pad8)")
(net 36 "Net-(J4-Pad9)")
(net 37 "Net-(J4-Pad10)")
(net 38 "Net-(J4-Pad11)")
(net 39 "Net-(J4-Pad12)")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(clearance 0.3)
(trace_width 0.2)
(via_dia 0.8)
(via_drill 0.5)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net /Absicht_BITCH)
(add_net /SEL)
(add_net /~OE)
(add_net GND)
(add_net "Net-(J1-Pad1)")
(add_net "Net-(J1-Pad10)")
@ -301,50 +299,6 @@
)
)
(module Pin_Headers:Pin_Header_Straight_1x04_Pitch2.54mm (layer B.Cu) (tedit 5AA00FF6) (tstamp 5AA00905)
(at 160.02 124.46 180)
(descr "Through hole straight pin header, 1x04, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x04 2.54mm single row")
(path /5A9FFF5C)
(fp_text reference J3 (at 0 2.33 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Conn_01x04 (at 0 -9.95 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -8.89) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 -8.89) (end -1.27 -8.89) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -8.89) (end -1.27 0.635) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.33 -8.95) (end 1.33 -8.95) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end -1.33 -8.95) (layer B.SilkS) (width 0.12))
(fp_line (start 1.33 -1.27) (end 1.33 -8.95) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.8 1.8) (end -1.8 -9.4) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -9.4) (end 1.8 -9.4) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 -9.4) (end 1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 -3.81 450) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole circle (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 25 /SEL))
(pad 2 thru_hole oval (at 0 -2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 26 /~OE))
(pad 3 thru_hole oval (at 0 -5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 27 VCC))
(pad 4 thru_hole rect (at 0 -7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 28 GND))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x04_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm (layer B.Cu) (tedit 5AA01030) (tstamp 5AA00915)
(at 160.02 88.9 180)
(descr "Through hole straight pin header, 1x12, 2.54mm pitch, single row")
@ -375,29 +329,29 @@
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole circle (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 29 "Net-(J4-Pad1)"))
(net 28 "Net-(J4-Pad1)"))
(pad 2 thru_hole oval (at 0 -2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 30 "Net-(J4-Pad2)"))
(net 29 "Net-(J4-Pad2)"))
(pad 3 thru_hole oval (at 0 -5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 31 "Net-(J4-Pad3)"))
(net 30 "Net-(J4-Pad3)"))
(pad 4 thru_hole oval (at 0 -7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 32 "Net-(J4-Pad4)"))
(net 31 "Net-(J4-Pad4)"))
(pad 5 thru_hole oval (at 0 -10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 33 "Net-(J4-Pad5)"))
(net 32 "Net-(J4-Pad5)"))
(pad 6 thru_hole oval (at 0 -12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 34 "Net-(J4-Pad6)"))
(net 33 "Net-(J4-Pad6)"))
(pad 7 thru_hole oval (at 0 -15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 35 /Absicht_BITCH))
(net 34 /Absicht_BITCH))
(pad 8 thru_hole oval (at 0 -17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 36 "Net-(J4-Pad8)"))
(net 35 "Net-(J4-Pad8)"))
(pad 9 thru_hole oval (at 0 -20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 37 "Net-(J4-Pad9)"))
(net 36 "Net-(J4-Pad9)"))
(pad 10 thru_hole oval (at 0 -22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 38 "Net-(J4-Pad10)"))
(net 37 "Net-(J4-Pad10)"))
(pad 11 thru_hole oval (at 0 -25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 39 "Net-(J4-Pad11)"))
(net 38 "Net-(J4-Pad11)"))
(pad 12 thru_hole oval (at 0 -27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 40 "Net-(J4-Pad12)"))
(net 39 "Net-(J4-Pad12)"))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x12_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@ -406,7 +360,7 @@
)
(module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer F.Cu) (tedit 58CC8F64) (tstamp 5AA00929)
(at 152.4 81.28)
(at 153.162 76.708)
(descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5A9FF14C)
@ -443,31 +397,31 @@
(pad 3 smd rect (at -2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 13 "Net-(J2-Pad1)"))
(pad 4 smd rect (at -2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 29 "Net-(J4-Pad1)"))
(net 28 "Net-(J4-Pad1)"))
(pad 5 smd rect (at -2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 2 "Net-(J1-Pad2)"))
(pad 6 smd rect (at -2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 14 "Net-(J2-Pad2)"))
(pad 7 smd rect (at -2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 30 "Net-(J4-Pad2)"))
(net 29 "Net-(J4-Pad2)"))
(pad 8 smd rect (at -2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 28 GND))
(net 27 GND))
(pad 9 smd rect (at 2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 32 "Net-(J4-Pad4)"))
(net 31 "Net-(J4-Pad4)"))
(pad 10 smd rect (at 2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 16 "Net-(J2-Pad4)"))
(pad 11 smd rect (at 2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 4 "Net-(J1-Pad4)"))
(pad 12 smd rect (at 2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 31 "Net-(J4-Pad3)"))
(net 30 "Net-(J4-Pad3)"))
(pad 13 smd rect (at 2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 15 "Net-(J2-Pad3)"))
(pad 14 smd rect (at 2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 "Net-(J1-Pad3)"))
(pad 15 smd rect (at 2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 26 /~OE))
(net 27 GND))
(pad 16 smd rect (at 2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 27 VCC))
(net 26 VCC))
(model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@ -513,31 +467,31 @@
(pad 3 smd rect (at -2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 17 "Net-(J2-Pad5)"))
(pad 4 smd rect (at -2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 33 "Net-(J4-Pad5)"))
(net 32 "Net-(J4-Pad5)"))
(pad 5 smd rect (at -2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 "Net-(J1-Pad6)"))
(pad 6 smd rect (at -2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 18 "Net-(J2-Pad6)"))
(pad 7 smd rect (at -2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 34 "Net-(J4-Pad6)"))
(net 33 "Net-(J4-Pad6)"))
(pad 8 smd rect (at -2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 28 GND))
(net 27 GND))
(pad 9 smd rect (at 2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 36 "Net-(J4-Pad8)"))
(net 35 "Net-(J4-Pad8)"))
(pad 10 smd rect (at 2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 20 "Net-(J2-Pad8)"))
(pad 11 smd rect (at 2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 8 "Net-(J1-Pad8)"))
(pad 12 smd rect (at 2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 35 /Absicht_BITCH))
(net 34 /Absicht_BITCH))
(pad 13 smd rect (at 2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 19 "Net-(J2-Pad7)"))
(pad 14 smd rect (at 2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 7 "Net-(J1-Pad7)"))
(pad 15 smd rect (at 2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 26 /~OE))
(net 27 GND))
(pad 16 smd rect (at 2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 27 VCC))
(net 26 VCC))
(model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@ -546,7 +500,7 @@
)
(module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer F.Cu) (tedit 58CC8F64) (tstamp 5AA00951)
(at 152.4 124.46)
(at 151.13 126.492)
(descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5A9FFD36)
@ -583,31 +537,31 @@
(pad 3 smd rect (at -2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 21 "Net-(J2-Pad9)"))
(pad 4 smd rect (at -2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 37 "Net-(J4-Pad9)"))
(net 36 "Net-(J4-Pad9)"))
(pad 5 smd rect (at -2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 10 "Net-(J1-Pad10)"))
(pad 6 smd rect (at -2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 22 "Net-(J2-Pad10)"))
(pad 7 smd rect (at -2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 38 "Net-(J4-Pad10)"))
(net 37 "Net-(J4-Pad10)"))
(pad 8 smd rect (at -2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 28 GND))
(net 27 GND))
(pad 9 smd rect (at 2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 40 "Net-(J4-Pad12)"))
(net 39 "Net-(J4-Pad12)"))
(pad 10 smd rect (at 2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 24 "Net-(J2-Pad12)"))
(pad 11 smd rect (at 2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(J1-Pad12)"))
(pad 12 smd rect (at 2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 39 "Net-(J4-Pad11)"))
(net 38 "Net-(J4-Pad11)"))
(pad 13 smd rect (at 2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 23 "Net-(J2-Pad11)"))
(pad 14 smd rect (at 2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 11 "Net-(J1-Pad11)"))
(pad 15 smd rect (at 2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 26 /~OE))
(net 27 GND))
(pad 16 smd rect (at 2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 27 VCC))
(net 26 VCC))
(model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@ -615,4 +569,671 @@
)
)
(module Pin_Headers:Pin_Header_Straight_1x03 (layer B.Cu) (tedit 0) (tstamp 5AA268BF)
(at 160.02 132.08)
(descr "Through hole pin header")
(tags "pin header")
(path /5AA1537F)
(fp_text reference P1 (at 0 5.1) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value CONN_01X03 (at 0 3.1) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.75 1.75) (end -1.75 -6.85) (layer B.CrtYd) (width 0.05))
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44
boards/mux12/mux12.sch
View File

@ -3,7 +3,6 @@ LIBS:power
LIBS:device
LIBS:switches
LIBS:relays
LIBS:motors
LIBS:transistors
LIBS:conn
LIBS:linear
@ -102,17 +101,6 @@ F 3 "" H 6550 3300 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L Conn_01x04 J3
U 1 1 5A9FFF5C
P 1750 5900
F 0 "J3" H 1750 6100 50 0000 C CNN
F 1 "Conn_01x04" H 1750 5600 50 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Straight_1x04_Pitch2.54mm" H 1750 5900 50 0001 C CNN
F 3 "" H 1750 5900 50 0001 C CNN
1 1750 5900
-1 0 0 -1
$EndComp
$Comp
L 74LS257 U1
U 1 1 5A9FF14C
P 4000 2200
@ -135,9 +123,9 @@ Text Label 3000 4000 0 60 ~ 0
~OE
Text Label 3000 2750 0 60 ~ 0
~OE
Text Label 2350 5900 0 60 ~ 0
Text Label 3400 5850 0 60 ~ 0
~OE
Text Label 2250 5800 0 60 ~ 0
Text Label 2250 5900 0 60 ~ 0
SEL
$Comp
L VCC #PWR01
@ -196,9 +184,7 @@ Wire Wire Line
Wire Wire Line
1950 6000 2550 6000
Wire Wire Line
1950 5800 2250 5800
Wire Wire Line
1950 5900 2350 5900
1950 5900 2250 5900
Wire Wire Line
3000 5150 3250 5150
Wire Wire Line
@ -437,4 +423,28 @@ F 3 "" H 5200 5750 50 0001 C CNN
1 5200 5750
-1 0 0 1
$EndComp
$Comp
L CONN_01X03 P1
U 1 1 5AA1537F
P 1750 6000
F 0 "P1" H 1750 6200 50 0000 C CNN
F 1 "CONN_01X03" V 1850 6000 50 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Straight_1x03" H 1750 6000 50 0001 C CNN
F 3 "" H 1750 6000 50 0000 C CNN
1 1750 6000
-1 0 0 1
$EndComp
$Comp
L GND #PWR07
U 1 1 5AA15424
P 3400 5950
F 0 "#PWR07" H 3400 5700 50 0001 C CNN
F 1 "GND" H 3400 5800 50 0000 C CNN
F 2 "" H 3400 5950 50 0000 C CNN
F 3 "" H 3400 5950 50 0000 C CNN
1 3400 5950
1 0 0 -1
$EndComp
Wire Wire Line
3400 5850 3400 5950
$EndSCHEMATC