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Create 6 bit version for two XC9536XL CPLDs

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Tested with two BitConnector breakout boards [1].

[1]: https://github.com/1ux/BitConnector
This commit is contained in:
Klemens Schölhorn 2020-02-24 22:15:34 +01:00 committed by 1ux
parent 13460a2bc1
commit 29bb72c4ff
5 changed files with 55 additions and 63 deletions
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44
firmware/alu/CPLD1.ucf
View File

@ -1,33 +1,27 @@
NET "func(0)" LOC = "43"; NET "func(0)" LOC = "27";
NET "func(1)" LOC = "44"; NET "func(1)" LOC = "28";
NET "func(2)" LOC = "1"; NET "func(2)" LOC = "29";
NET "func(3)" LOC = "2"; NET "func(3)" LOC = "30";
NET "accu(0)" LOC = "27"; NET "accu(0)" LOC = "31";
NET "accu(1)" LOC = "28"; NET "accu(1)" LOC = "32";
NET "accu(2)" LOC = "29"; NET "accu(2)" LOC = "34";
NET "accu(3)" LOC = "30"; NET "accu(3)" LOC = "36";
NET "accu(4)" LOC = "31"; NET "accu(4)" LOC = "37";
NET "accu(5)" LOC = "32"; NET "accu(5)" LOC = "38";
NET "accu(6)" LOC = "37";
NET "accu(7)" LOC = "38";
NET "ram(0)" LOC = "39"; NET "ram(0)" LOC = "39";
NET "ram(1)" LOC = "40"; NET "ram(1)" LOC = "40";
NET "ram(2)" LOC = "41"; NET "ram(2)" LOC = "41";
NET "ram(3)" LOC = "42"; NET "ram(3)" LOC = "42";
NET "ram(4)" LOC = "5"; NET "ram(4)" LOC = "43";
NET "ram(5)" LOC = "6"; NET "ram(5)" LOC = "44";
NET "ram(6)" LOC = "7";
NET "ram(7)" LOC = "8";
NET "result(0)" LOC = "22"; NET "result(0)" LOC = "23";
NET "result(1)" LOC = "21"; NET "result(1)" LOC = "22";
NET "result(2)" LOC = "20"; NET "result(2)" LOC = "21";
NET "result(3)" LOC = "19"; NET "result(3)" LOC = "20";
NET "result(4)" LOC = "18"; NET "result(4)" LOC = "19";
NET "result(5)" LOC = "16"; NET "result(5)" LOC = "18";
NET "result(6)" LOC = "14";
NET "result(7)" LOC = "13";
NET "carry_out" LOC = "3"; NET "carry_out" LOC = "16";

8
firmware/alu/CPLD1.vhd
View File

@ -5,9 +5,9 @@ use ieee.std_logic_1164.all;
entity CPLD1 is entity CPLD1 is
port ( port (
func: in std_logic_vector(3 downto 0); func: in std_logic_vector(3 downto 0);
accu: in std_logic_vector(7 downto 0); accu: in std_logic_vector(5 downto 0);
ram: in std_logic_vector(7 downto 0); ram: in std_logic_vector(5 downto 0);
result: out std_logic_vector(7 downto 0); result: out std_logic_vector(5 downto 0);
carry_out: out std_logic carry_out: out std_logic
); );
end CPLD1; end CPLD1;
@ -16,7 +16,7 @@ architecture rtl of CPLD1 is
begin begin
alu: entity work.alu generic map ( alu: entity work.alu generic map (
WIDTH => 8, WIDTH => 6,
FIRST => true FIRST => true
) port map ( ) port map (
func => func, func => func,

44
firmware/alu/CPLD2.ucf
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@ -1,33 +1,27 @@
NET "func(0)" LOC = "44"; NET "func(0)" LOC = "27";
NET "func(1)" LOC = "43"; NET "func(1)" LOC = "28";
NET "func(2)" LOC = "42"; NET "func(2)" LOC = "29";
NET "func(3)" LOC = "41"; NET "func(3)" LOC = "30";
NET "accu(8)" LOC = "27"; NET "accu(6)" LOC = "31";
NET "accu(9)" LOC = "28"; NET "accu(7)" LOC = "32";
NET "accu(10)" LOC = "29"; NET "accu(8)" LOC = "34";
NET "accu(11)" LOC = "30"; NET "accu(9)" LOC = "36";
NET "accu(12)" LOC = "31"; NET "accu(10)" LOC = "37";
NET "accu(13)" LOC = "32"; NET "accu(11)" LOC = "38";
NET "accu(14)" LOC = "37";
NET "accu(15)" LOC = "38";
NET "ram(8)" LOC = "39"; NET "ram(6)" LOC = "39";
NET "ram(9)" LOC = "40"; NET "ram(7)" LOC = "40";
NET "ram(10)" LOC = "2"; NET "ram(8)" LOC = "41";
NET "ram(11)" LOC = "3"; NET "ram(9)" LOC = "42";
NET "ram(12)" LOC = "5"; NET "ram(10)" LOC = "43";
NET "ram(13)" LOC = "6"; NET "ram(11)" LOC = "44";
NET "ram(14)" LOC = "7";
NET "ram(15)" LOC = "8";
NET "result(6)" LOC = "23";
NET "result(7)" LOC = "22";
NET "result(8)" LOC = "21"; NET "result(8)" LOC = "21";
NET "result(9)" LOC = "20"; NET "result(9)" LOC = "20";
NET "result(10)" LOC = "19"; NET "result(10)" LOC = "19";
NET "result(11)" LOC = "18"; NET "result(11)" LOC = "18";
NET "result(12)" LOC = "16";
NET "result(13)" LOC = "14";
NET "result(14)" LOC = "13";
NET "result(15)" LOC = "12";
NET "carry_in" LOC = "33"; NET "carry_in" LOC = "16";

8
firmware/alu/CPLD2.vhd
View File

@ -5,10 +5,10 @@ use ieee.std_logic_1164.all;
entity CPLD2 is entity CPLD2 is
port ( port (
func: in std_logic_vector(3 downto 0); func: in std_logic_vector(3 downto 0);
accu: in std_logic_vector(15 downto 8); accu: in std_logic_vector(11 downto 6);
ram: in std_logic_vector(15 downto 8); ram: in std_logic_vector(11 downto 6);
carry_in: in std_logic; carry_in: in std_logic;
result: out std_logic_vector(15 downto 8) result: out std_logic_vector(11 downto 6)
); );
end CPLD2; end CPLD2;
@ -16,7 +16,7 @@ architecture rtl of CPLD2 is
begin begin
alu: entity work.alu generic map ( alu: entity work.alu generic map (
WIDTH => 8, WIDTH => 6,
FIRST => false FIRST => false
) port map ( ) port map (
func => func, func => func,

14
firmware/alu/alu.xise
View File

@ -42,6 +42,9 @@
<file xil_pn:name="CPLD2.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="CPLD2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="CPLD1.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files> </files>
<properties> <properties>
@ -61,7 +64,7 @@
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-36)" xil_pn:value="36" xil_pn:valueState="default"/> <property xil_pn:name="Collapsing Input Limit (2-36)" xil_pn:value="36" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/> <property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/> <property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="90" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@ -99,7 +102,7 @@
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/> <property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/> <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|CPLD2|rtl" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|CPLD2|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="CPLD2.vhd" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="CPLD2.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/CPLD2" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/CPLD2" xil_pn:valueState="non-default"/>
@ -119,8 +122,8 @@
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Local Macrocell Feedback" xil_pn:value="On" xil_pn:valueState="default"/> <property xil_pn:name="Local Macrocell Feedback" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/> <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/> <property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
@ -152,7 +155,7 @@
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/> <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="VQ44" xil_pn:valueState="non-default"/> <property xil_pn:name="Package" xil_pn:value="VQ44" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pin Feedback" xil_pn:value="On" xil_pn:valueState="default"/> <property xil_pn:name="Pin Feedback" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="CPLD2_map.v" xil_pn:valueState="default"/> <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="CPLD2_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="CPLD2_timesim.v" xil_pn:valueState="default"/> <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="CPLD2_timesim.v" xil_pn:valueState="default"/>
@ -250,6 +253,7 @@
<bindings> <bindings>
<binding xil_pn:location="/CPLD2" xil_pn:name="CPLD2.ucf"/> <binding xil_pn:location="/CPLD2" xil_pn:name="CPLD2.ucf"/>
<binding xil_pn:location="/CPLD1" xil_pn:name="CPLD1.ucf"/>
</bindings> </bindings>
<libraries/> <libraries/>