Add top modules and pin constraints for the two ALU CPLDs

This commit is contained in:
2018-07-26 21:44:35 +02:00
parent 7202b01c93
commit 1116ec8a50
7 changed files with 170 additions and 24 deletions

View File

@ -87,6 +87,7 @@ xilinxsim.ini
# cpld
/main_html/
*_html/
*.gyd
*.jed
*.mfd
@ -96,4 +97,6 @@ xilinxsim.ini
*.vm6
*.xml
*.err
*.tim
*.tspec