Add top modules and pin constraints for the two ALU CPLDs
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3
firmware/alu/.gitignore
vendored
3
firmware/alu/.gitignore
vendored
@ -87,6 +87,7 @@ xilinxsim.ini
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# cpld
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/main_html/
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*_html/
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*.gyd
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*.jed
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*.mfd
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@ -96,4 +97,6 @@ xilinxsim.ini
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*.vm6
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*.xml
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*.err
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*.tim
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*.tspec
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