Add toy alu with initial testbench

firmware/alu/tests/toy_16.vhd

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+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity toy_16 is
+end toy_16;
+
+architecture test of toy_16 is
+
+    constant period: time := 1us;
+
+    component main
+        port (
+            func: in std_logic_vector(3 downto 0);
+            accu: in std_logic_vector(7 downto 0);
+            ram: in std_logic_vector(7 downto 0);
+            carry_in: in std_logic;
+            result: out std_logic_vector(7 downto 0);
+            carry_out: out std_logic
+        );
+    end component;
+
+    --Inputs
+    signal func: std_logic_vector(3 downto 0) := (others => '0');
+    signal accu: std_logic_vector(15 downto 0) := (others => '0');
+    signal ram: std_logic_vector(15 downto 0) := (others => '0');
+    signal carry_in: std_logic := '0';
+
+    --Outputs
+    signal result: std_logic_vector(15 downto 0);
+    signal carry_out: std_logic;
+
+    -- Internal signals
+    signal carry_propagation: std_logic;
+
+    -- Test constants
+    constant A: std_logic_vector(15 downto 0) := "1010101010101010";
+    constant B: std_logic_vector(15 downto 0) := "1100110011001100";
+
+    -- Info String (driven by procedure in test_process)
+    signal info_string: string(1 to 10);
+
+begin
+
+    alu1: main port map (
+        func => func,
+        accu => accu(7 downto 0),
+        ram => ram(7 downto 0),
+        carry_in => '0',
+        result => result(7 downto 0),
+        carry_out => carry_propagation
+    );
+
+    alu2: main port map (
+        func => func,
+        accu => accu(15 downto 8),
+        ram => ram(15 downto 8),
+        carry_in => carry_propagation,
+        result => result(15 downto 8),
+        carry_out => open
+    );
+
+    test_process: process
+        procedure info(info: string) is
+        begin
+            info_string <= (others => ' ');
+            info_string(1 to info'length) <= info;
+        end procedure;
+    begin
+        --
+        -- logic tests
+        --
+        accu <= A; ram <= B; carry_in <= '0';
+
+        info("STORE");
+        func <= "0000";
+        wait for period;
+        assert result = A report "STORE failed";
+
+        info("LOAD");
+        func <= "0001";
+        wait for period;
+        assert result = B report "LOAD failed";
+
+        info("OR");
+        func <= "0101";
+        wait for period;
+        assert result = (A or B) report "OR failed";
+
+        info("AND");
+        func <= "0110";
+        wait for period;
+        assert result = (A and B) report "AND failed";
+
+        info("XOR");
+        func <= "0111";
+        wait for period;
+        assert result = (A xor B) report "XOR failed";
+
+        info("NOT");
+        func <= "1000";
+        wait for period;
+        assert result = not A report "NOT failed";
+
+        info("ZERO");
+        func <= "1011";
+        wait for period;
+        assert result = "0000000000000000" report "ZERO failed";
+
+        --
+        -- arithmatic tests
+        --
+
+        info("ADD");
+        accu <= "0100010011110011";
+        ram <=  "0011100010101010"; carry_in <= '0';
+        func <= "0011";
+        wait for period;
+        assert result = "0111110110011101" report "ADD failed";
+
+        info("SUB");
+        accu <= "0100010000110011";
+        ram <=  "0011100000101010"; carry_in <= '0';
+        func <= "0100";
+        wait for period;
+        assert result = "0000110000001001" report "SUB failed";
+
+        info("SUB-B");
+        accu <= "0100010010110011";
+        ram <=  "0011100011101010"; carry_in <= '0';
+        func <= "0100";
+        wait for period;
+        assert result = "0000101111001001" report "SUB failed";
+
+        -- terminate test
+        wait;
+
+    end process;
+
+end test;