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riscv
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workstation
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workstation
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project
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ise
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Klemens Schölhorn
ce76d77699
Add missing module to the ISE project and ignore generated MIG-Core
2018-06-05 17:15:48 +02:00
..
.gitignore
Add missing module to the ISE project and ignore generated MIG-Core
2018-06-05 17:15:48 +02:00
ml507_ddr2_clock.v
Import clock definition files
2018-06-05 16:04:27 +02:00
ml507_dvi_clock.v
Import clock definition files
2018-06-05 16:04:27 +02:00
ml507_sys_clock.v
Import clock definition files
2018-06-05 16:04:27 +02:00
risc-v-workstation.xise
Add missing module to the ISE project and ignore generated MIG-Core
2018-06-05 17:15:48 +02:00
