Klemens Schölhorn
e1bf43fa47
We cannot add the full repository here, because it contains the mig core, which is not allowed to be redistributed publicy.
242 lines
9.2 KiB
VHDL
242 lines
9.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity memory_controller is
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port (
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-- clocks
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sys_clk0: in std_logic;
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sys_clk90: in std_logic;
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sys_clkdiv0: in std_logic;
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sys_clk_locked: in std_logic;
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sys_clk_idelay: in std_logic;
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sys_reset: in std_logic;
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-- read and write requests
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request_addr: in std_logic_vector(27 downto 0); -- 256 MiB, no CS (SR)
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request_type: in std_logic; -- read (1) or write (0)
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request_data: in std_logic_vector(255 downto 0);
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request_mask: in std_logic_vector(31 downto 0);
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request_valid: in std_logic;
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request_ready: out std_logic;
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-- read responses
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response_data: out std_logic_vector(255 downto 0);
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response_valid: out std_logic; -- only asserted for one cycle, no ready
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-- physical ddr2 interface
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ddr2_dq: inout std_logic_vector(63 downto 0);
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ddr2_a: out std_logic_vector(12 downto 0);
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ddr2_ba: out std_logic_vector(1 downto 0);
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ddr2_ras_n: out std_logic;
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ddr2_cas_n: out std_logic;
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ddr2_we_n: out std_logic;
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ddr2_cs_n: out std_logic_vector(0 downto 0);
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ddr2_odt: out std_logic_vector(0 downto 0);
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ddr2_cke: out std_logic_vector(0 downto 0);
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ddr2_dm: out std_logic_vector(7 downto 0);
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ddr2_dqs: inout std_logic_vector(7 downto 0);
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ddr2_dqs_n: inout std_logic_vector(7 downto 0);
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ddr2_ck: out std_logic_vector(1 downto 0);
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ddr2_ck_n: out std_logic_vector(1 downto 0)
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);
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end memory_controller;
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architecture rtl of memory_controller is
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signal clk: std_logic;
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signal reset_p: std_logic;
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type request_states is (
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REQ_IDLE,
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REQ_WRITE
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);
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signal request_state: request_states := REQ_IDLE;
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type response_states is (
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RES_IDLE,
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RES_WAIT_SECOND
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);
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signal response_state: response_states := RES_IDLE;
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signal ram_init_done: std_logic;
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signal ram_address: std_logic_vector(30 downto 0);
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signal ram_command: std_logic_vector(2 downto 0);
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signal ram_data_in: std_logic_vector(127 downto 0);
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signal ram_mask_in: std_logic_vector(15 downto 0);
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signal ram_data_out: std_logic_vector(127 downto 0);
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signal ram_enq_address: std_logic;
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signal ram_enq_data: std_logic;
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signal ram_address_afull: std_logic;
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signal ram_data_afull: std_logic;
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signal ram_data_valid: std_logic;
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signal is_request_ready: std_logic;
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signal data_in_high: std_logic_vector(127 downto 0);
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signal mask_in_high: std_logic_vector(15 downto 0);
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signal data_out_low: std_logic_vector(127 downto 0);
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begin
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reset_p <= not sys_reset;
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-- the lowest three bits pick one of the 8 bytes inside the 64b ram width
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ram_address <= "000000" & request_addr(27 downto 3);
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-- WRITE is 000 and READ is 001
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ram_command <= "00" & request_type;
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-- we directly pass the lower half to the mig fifo and only store the
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-- upper half for writing on a second cycle (this works because we can
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-- still write 12 words to the fifo when the *almost full* signal is
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-- asserted by the mig)
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ram_data_in <= request_data(127 downto 0) when request_state = REQ_IDLE else
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data_in_high;
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ram_mask_in <= request_mask(15 downto 0) when request_state = REQ_IDLE else
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mask_in_high;
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-- to directly pass data to the fifos (see above) we also have to enable
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-- the fifo write signals combinatorially, otherwise we miss the first part
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ram_enq_address <= is_request_ready and request_valid;
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-- the data write signal is only high for write requests and also has to
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-- be kept high for a second cycle to write the upper half of the data
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ram_enq_data <= '1' when ( (is_request_ready and request_valid) = '1' and
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(request_type = '0')
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) or (request_state = REQ_WRITE)
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else '0';
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-- we are only ready if we can write to *both* fifos and everything is
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-- fully initialized (we could theoretically only look at the address fifo
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-- for read requests)
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is_request_ready <= '1' when (ram_init_done = '1') and
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(ram_address_afull = '0') and
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(ram_data_afull = '0') and
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(request_state = REQ_IDLE)
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else '0';
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request_ready <= is_request_ready;
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input: process(clk, sys_reset)
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begin
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if sys_reset = '1' then
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request_state <= REQ_IDLE;
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elsif rising_edge(clk) then
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case request_state is
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when REQ_IDLE =>
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if is_request_ready = '1' and request_valid = '1' then
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if request_type = '1' then -- READ
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request_state <= REQ_IDLE;
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else -- WRITE
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data_in_high <= request_data(255 downto 128);
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mask_in_high <= request_mask(31 downto 16);
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request_state <= REQ_WRITE;
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end if;
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end if;
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when REQ_WRITE =>
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request_state <= REQ_IDLE;
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end case;
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end if;
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end process input;
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-- we pass the higher half directly from the mig
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response_data <= ram_data_out & data_out_low;
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-- read_valid only asserted for one cycle, must be read immediately
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response_valid <= '1' when (response_state = RES_WAIT_SECOND) and
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(ram_data_valid = '1')
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else '0';
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output: process(clk, sys_reset)
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begin
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if sys_reset = '1' then
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response_state <= RES_IDLE;
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elsif rising_edge(clk) then
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case response_state is
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when RES_IDLE =>
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if ram_data_valid = '1' then
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data_out_low <= ram_data_out;
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response_state <= RES_WAIT_SECOND;
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end if;
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when RES_WAIT_SECOND =>
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if ram_data_valid = '1' then
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response_state <= RES_IDLE;
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end if;
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end case;
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end if;
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end process output;
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ddr2_controller: entity work.ddr2_controller port map (
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clk0 => sys_clk0,
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clk90 => sys_clk90,
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clkdiv0 => sys_clkdiv0,
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clk200 => sys_clk_idelay,
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locked => sys_clk_locked,
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sys_rst_n => reset_p,
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rst0_tb => open,
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clk0_tb => clk,
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phy_init_done => ram_init_done,
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app_wdf_afull => ram_data_afull,
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app_af_afull => ram_address_afull,
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rd_data_valid => ram_data_valid,
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app_wdf_wren => ram_enq_data,
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app_af_wren => ram_enq_address,
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app_af_addr => ram_address,
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app_af_cmd => ram_command,
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rd_data_fifo_out => ram_data_out,
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app_wdf_data => ram_data_in,
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app_wdf_mask_data => ram_mask_in,
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ddr2_dq => ddr2_dq,
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ddr2_a => ddr2_a,
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ddr2_ba => ddr2_ba,
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ddr2_ras_n => ddr2_ras_n,
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ddr2_cas_n => ddr2_cas_n,
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ddr2_we_n => ddr2_we_n,
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ddr2_cs_n => ddr2_cs_n,
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ddr2_odt => ddr2_odt,
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ddr2_cke => ddr2_cke,
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ddr2_dm => ddr2_dm,
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ddr2_dqs => ddr2_dqs,
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ddr2_dqs_n => ddr2_dqs_n,
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ddr2_ck => ddr2_ck,
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ddr2_ck_n => ddr2_ck_n
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);
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--~ sys_clk_p : in std_logic;
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--~ sys_clk_n : in std_logic;
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--~ clk200_p : in std_logic;
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--~ clk200_n : in std_logic;
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--~ sys_rst_n : in std_logic;
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--~ rst0_tb : out std_logic;
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--~ clk0_tb : out std_logic;
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--~ phy_init_done : out std_logic;
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--~ app_wdf_afull : out std_logic;
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--~ app_af_afull : out std_logic;
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--~ app_wdf_wren : in std_logic;
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--~ app_af_wren : in std_logic;
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--~ app_af_addr : in std_logic_vector(30 downto 0);
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--~ app_af_cmd : in std_logic_vector(2 downto 0);
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--~ app_wdf_data : in std_logic_vector(127 downto 0);
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--~ app_wdf_mask_data : in std_logic_vector(15 downto 0);
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--~ rd_data_fifo_out : out std_logic_vector(127 downto 0);
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--~ rd_data_valid : out std_logic;
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--~ ddr2_dq : inout std_logic_vector(63 downto 0);
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--~ ddr2_a : out std_logic_vector(12 downto 0);
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--~ ddr2_ba : out std_logic_vector(1 downto 0);
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--~ ddr2_ras_n : out std_logic;
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--~ ddr2_cas_n : out std_logic;
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--~ ddr2_we_n : out std_logic;
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--~ ddr2_cs_n : out std_logic_vector(0 downto 0);
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--~ ddr2_odt : out std_logic_vector(0 downto 0);
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--~ ddr2_cke : out std_logic_vector(0 downto 0);
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--~ ddr2_dm : out std_logic_vector(7 downto 0);
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--~ ddr2_dqs : inout std_logic_vector(7 downto 0);
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--~ ddr2_dqs_n : inout std_logic_vector(7 downto 0);
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--~ ddr2_ck : out std_logic_vector(1 downto 0);
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--~ ddr2_ck_n : out std_logic_vector(1 downto 0)
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end rtl;
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