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ce76d77699
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Add missing module to the ISE project and ignore generated MIG-Core
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2018-06-05 17:15:48 +02:00 |
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dfd2d2ac9b
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Use new ise virtex-6 parser and set SYNTHESIS verilog constant
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2018-06-05 16:10:42 +02:00 |
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fbab58fa13
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Add constraint files to the ise project
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2018-06-05 16:04:27 +02:00 |
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f9b72609f1
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Import clock definition files
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2018-06-05 16:04:27 +02:00 |
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55cd91d4da
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Add basic ise project with relative paths
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2018-06-05 16:04:27 +02:00 |
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