119 lines
2.7 KiB
Plaintext
119 lines
2.7 KiB
Plaintext
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "freechips,rocketchip-unknown-dev";
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model = "freechips,rocketchip-unknown";
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aliases {
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serial0 = &L8;
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};
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L15: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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L5: cpu@0 {
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clock-frequency = <60000000>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <4096>;
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d-tlb-sets = <1>;
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d-tlb-size = <4>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <4096>;
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i-tlb-sets = <1>;
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i-tlb-size = <4>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L12>;
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reg = <0>;
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riscv,isa = "rv64imafdc";
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status = "okay";
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timebase-frequency = <1000000>;
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tlb-split;
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L3: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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L12: memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x10000000>;
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};
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L14: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
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ranges;
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sysclk: sysclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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};
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L1: clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&L3 3 &L3 7>;
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reg = <0x2000000 0x10000>;
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reg-names = "control";
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};
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L2: debug-controller@0 {
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compatible = "sifive,debug-013", "riscv,debug-013";
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interrupts-extended = <&L3 65535>;
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reg = <0x0 0x1000>;
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reg-names = "control";
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};
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L7: error-device@3000 {
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compatible = "sifive,error0";
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reg = <0x3000 0x1000>;
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reg-names = "mem";
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};
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L11: gpio@64002000 {
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compatible = "sifive,gpio0";
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interrupt-parent = <&L0>;
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interrupts = <3 4 5 6 7 8 9 10>;
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reg = <0x64002000 0x1000>;
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reg-names = "control";
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};
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L0: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended = <&L3 11 &L3 9>;
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reg = <0xc000000 0x4000000>;
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reg-names = "control";
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riscv,max-priority = <7>;
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riscv,ndev = <10>;
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};
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L6: rom@10000 {
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compatible = "sifive,maskrom0";
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reg = <0x10000 0x2000>;
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reg-names = "mem";
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};
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L8: serial@64000000 {
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compatible = "sifive,uart0";
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interrupt-parent = <&L0>;
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interrupts = <1>;
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reg = <0x64000000 0x1000>;
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reg-names = "control";
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clocks = <&sysclk 0>;
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};
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L10: spi@64001000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&L0>;
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interrupts = <2>;
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reg = <0x64001000 0x1000>;
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reg-names = "control";
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clocks = <&sysclk 0>;
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};
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L9: serial@64003000 {
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compatible = "klemens,terminal0";
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reg = <0x64003000 0x1000>;
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reg-names = "control";
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clocks = <&sysclk 0>;
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};
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};
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};
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