82 lines
1.8 KiB
VHDL
82 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity main is
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port (
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clk: in std_logic;
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dvi_d: out std_logic_vector(11 downto 0);
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dvi_clk_p: out std_logic;
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dvi_clk_n: out std_logic;
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dvi_hsync: out std_logic;
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dvi_vsync: out std_logic;
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dvi_de: out std_logic;
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dvi_reset: out std_logic;
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i2c_scl: inout std_logic;
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i2c_sda: inout std_logic;
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ps2_scl: inout std_logic;
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ps2_sda: inout std_logic;
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switch_center: in std_logic;
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rotary_up: in std_logic;
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rotary_down: in std_logic;
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rotary_push: in std_logic;
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led: out std_logic_vector(7 downto 0)
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);
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end main;
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architecture syn of main is
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constant clk_vga_f: integer := 48_000_000;
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signal clk_vga: std_logic;
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signal reset: std_logic;
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begin
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reset <= switch_center;
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-- convert the 100MHz to a 48MHz pixel clock
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clock_source: entity work.clock_source port map (
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CLKIN_IN => clk,
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CLKFX_OUT => clk_vga
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);
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terminal: entity work.terminal generic map (
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clk_f => clk_vga_f
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) port map (
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clk => clk_vga,
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reset => reset,
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write_enable => '0',
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write_data => x"00",
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dvi_d => dvi_d,
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dvi_clk_p => dvi_clk_p,
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dvi_clk_n => dvi_clk_n,
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dvi_hsync => dvi_hsync,
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dvi_vsync => dvi_vsync,
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dvi_de => dvi_de,
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dvi_reset => dvi_reset,
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i2c_scl => i2c_scl,
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i2c_sda => i2c_sda
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);
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keyboard_i: entity work.keyboard generic map (
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input_clk => clk_vga_f
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) port map (
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clk => clk_vga,
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reset => reset,
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bytes_received => led(5 downto 0),
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ps2_scl => ps2_scl,
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ps2_sda => ps2_sda
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);
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led(7) <= reset;
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led(6) <= '0';
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end syn;
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