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Add the actual init sequence for clocks <= 65 MHz

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This commit is contained in:
Klemens Schölhorn 2017-11-23 02:12:25 +01:00
parent da4e8230c5
commit ea6b3418de
2 changed files with 36 additions and 23 deletions
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9
init_ch7301c.ucf
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@ -6,15 +6,6 @@ NET "i2c_scl" LOC = U27;
NET "i2c_sda" LOC = T29;
NET "dvi_reset" LOC = AK6;
NET "dip(0)" LOC = AC24;
NET "dip(1)" LOC = AC25;
NET "dip(2)" LOC = AE26;
NET "dip(3)" LOC = AE27;
NET "dip(4)" LOC = AF26;
NET "dip(5)" LOC = AF25;
NET "dip(6)" LOC = AG27;
NET "dip(7)" LOC = U25;
NET "led(0)" LOC = H18;
NET "led(1)" LOC = L18;
NET "led(2)" LOC = G15;

50
init_ch7301c.vhd
View File

@ -23,7 +23,6 @@ entity init_ch7301c is
-- tmp
dvi_reset: out std_logic;
led: out std_logic_vector(7 downto 0);
dip: in std_logic_vector(7 downto 0);
led_n: out std_logic;
led_s: out std_logic;
led_c: out std_logic
@ -67,7 +66,7 @@ begin
-- ch7301c needs some time (>2µs) to init its i2c port after reset
constant max_delay: integer := input_clk / 200_000; -- 5µs
variable delay: integer range 0 to max_delay := 0;
variable busy_count: integer range 0 to 3 := 0;
variable busy_count: integer range 0 to 10 := 0;
begin
if reset = '1' then
delay := 0;
@ -101,25 +100,48 @@ begin
case busy_count is
when 0 =>
-- no command accepted yet, insert first one
-- start configure sequence
i2c_execute <= '1';
i2c_write <= '1';
i2c_address <= address;
i2c_data_in <= dip;
-- select register PM (power management)
i2c_data_in <= x"49";
when 1 =>
-- submit read command
i2c_write <= '0';
-- enable clock pll, dvi encoder and transmitter
i2c_data_in <= x"C0";
when 2 =>
-- read submitted, wait for results, no more commands
i2c_execute <= '0';
if i2c_busy = '0' then
led <= i2c_data_out;
busy_count := 3;
end if;
-- select register DC (DAC control)
i2c_data_in <= x"21";
when 3 =>
-- finished!
-- enable dac bypass and h/vsync outputs
i2c_data_in <= x"09";
when 4 =>
-- select register TPCP (PLL charge pump control)
i2c_data_in <= x"33";
when 5 =>
-- enable <= 65 MHz mode (datasheet table 10)
i2c_data_in <= x"08";
when 6 =>
-- select register TPD (PLL divider)
i2c_data_in <= x"34";
when 7 =>
-- enable <= 65 MHz mode (datasheet table 10)
i2c_data_in <= x"16";
when 8 =>
-- select register TPF (PLL filter)
i2c_data_in <= x"36";
when 9 =>
-- enable <= 65 MHz mode (datasheet table 10)
i2c_data_in <= x"60";
when 10 =>
-- no more commands
i2c_execute <= '0';
finished <= '1';
null;
end case;
else
delay := delay + 1;