riscv/terminal
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Make block ram entity generic over width and depth

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This commit is contained in:
Klemens Schölhorn 2018-04-25 22:55:39 +02:00
parent 20aa3137a8
commit 7cf0aa33c0
3 changed files with 21 additions and 13 deletions
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5
framebuffer.vhd
View File

@ -58,7 +58,10 @@ begin
read_address <= x(9 downto 3) & y(8 downto 3);
terminal_buffer: entity work.terminal_buffer port map (
terminal_buffer: entity work.ram_2port generic map (
WIDTH_BITS => 8,
DEPTH_BITS => 13
) port map (
clk => clk,
ra => read_address,
do => current_char,

21
terminal_buffer.vhd → ram_2port.vhd
View File

@ -4,19 +4,24 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity terminal_buffer is
entity ram_2port is
generic (
WIDTH_BITS: integer;
DEPTH_BITS: integer
);
port (
clk: in std_logic;
we: in std_logic;
wa: in std_logic_vector(12 downto 0);
ra: in std_logic_vector(12 downto 0);
di: in std_logic_vector(7 downto 0);
do: out std_logic_vector(7 downto 0)
wa: in std_logic_vector(DEPTH_BITS-1 downto 0);
ra: in std_logic_vector(DEPTH_BITS-1 downto 0);
di: in std_logic_vector(WIDTH_BITS-1 downto 0);
do: out std_logic_vector(WIDTH_BITS-1 downto 0)
);
end terminal_buffer;
end ram_2port;
architecture syn of terminal_buffer is
type ram_type is array((2**13 - 1) downto 0) of std_logic_vector(7 downto 0);
architecture syn of ram_2port is
type ram_type is array((2**DEPTH_BITS - 1) downto 0) of
std_logic_vector(WIDTH_BITS-1 downto 0);
signal RAM: ram_type;
signal read_a: std_logic_vector(ra'range);
begin

8
terminal.xise
View File

@ -52,10 +52,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="terminal_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="terminal.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
@ -64,6 +60,10 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="157"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="ram_2port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="157"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
</files>
<properties>