diff --git a/framebuffer.vhd b/framebuffer.vhd
index a74855b..8a9eb21 100644
--- a/framebuffer.vhd
+++ b/framebuffer.vhd
@@ -58,7 +58,10 @@ begin
 
     read_address <= x(9 downto 3) & y(8 downto 3);
 
-    terminal_buffer: entity work.terminal_buffer port map (
+    terminal_buffer: entity work.ram_2port generic map (
+        WIDTH_BITS => 8,
+        DEPTH_BITS => 13
+    ) port map (
         clk => clk,
         ra => read_address,
         do => current_char,
diff --git a/terminal_buffer.vhd b/ram_2port.vhd
similarity index 52%
rename from terminal_buffer.vhd
rename to ram_2port.vhd
index 796e22e..b4c4c43 100644
--- a/terminal_buffer.vhd
+++ b/ram_2port.vhd
@@ -4,19 +4,24 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.numeric_std.all;
 
-entity terminal_buffer is
+entity ram_2port is
+    generic (
+        WIDTH_BITS: integer;
+        DEPTH_BITS: integer
+    );
     port (
         clk: in std_logic;
         we: in std_logic;
-        wa: in std_logic_vector(12 downto 0);
-        ra: in std_logic_vector(12 downto 0);
-        di: in std_logic_vector(7 downto 0);
-        do: out std_logic_vector(7 downto 0)
+        wa: in std_logic_vector(DEPTH_BITS-1 downto 0);
+        ra: in std_logic_vector(DEPTH_BITS-1 downto 0);
+        di: in std_logic_vector(WIDTH_BITS-1 downto 0);
+        do: out std_logic_vector(WIDTH_BITS-1 downto 0)
     );
-end terminal_buffer;
+end ram_2port;
 
-architecture syn of terminal_buffer is
-    type ram_type is array((2**13 - 1) downto 0) of std_logic_vector(7 downto 0);
+architecture syn of ram_2port is
+    type ram_type is array((2**DEPTH_BITS - 1) downto 0) of
+                     std_logic_vector(WIDTH_BITS-1 downto 0);
     signal RAM: ram_type;
     signal read_a: std_logic_vector(ra'range);
 begin
diff --git a/terminal.xise b/terminal.xise
index e51e7d3..b984187 100644
--- a/terminal.xise
+++ b/terminal.xise
@@ -52,10 +52,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
-    <file xil_pn:name="terminal_buffer.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-    </file>
     <file xil_pn:name="terminal.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
@@ -64,6 +60,10 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="157"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
+    <file xil_pn:name="ram_2port.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="157"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
   </files>
 
   <properties>