Make terminal genericity opt-in for easier interfacing

main.vhd

@@ -45,9 +45,7 @@ begin
 		CLKFX_OUT => clk_vga
 	);
 
-    terminal: entity work.terminal generic map (
-        clk_f => clk_vga_f
-    ) port map (
+    terminal: entity work.terminal port map (
         clk => clk_vga,
         reset => reset,
 

terminal.vhd

@@ -9,7 +9,7 @@ use unisim.VComponents.all;
 
 entity terminal is
     generic (
-        clk_f: integer
+        clk_f: integer := 48_000_000
     );
     port (
         clk: in std_logic;