Make terminal genericity opt-in for easier interfacing

2018-04-25 23:47:50 +02:00
parent 7cf0aa33c0
commit 2f858a6764
2 changed files with 2 additions and 4 deletions
--- a/terminal.vhd
+++ b/terminal.vhd
@ -9,7 +9,7 @@ use unisim.VComponents.all;

 entity terminal is
    generic (
-        clk_f: integer
+        clk_f: integer := 48_000_000
    );
    port (
        clk: in std_logic;