Move vga and image creation entities into a new terminal entity
This commit is contained in:
parent
5f47c1327f
commit
0aad663c33
@ -17,7 +17,7 @@
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<files>
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<files>
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<file xil_pn:name="vga.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="vga.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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</file>
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</file>
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<file xil_pn:name="vga_test.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="vga_test.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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@ -27,39 +27,43 @@
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</file>
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</file>
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<file xil_pn:name="i2c_master.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="i2c_master.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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</file>
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<file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
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</file>
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</file>
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<file xil_pn:name="ipcore_dir/clock_source.xaw" xil_pn:type="FILE_XAW">
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<file xil_pn:name="ipcore_dir/clock_source.xaw" xil_pn:type="FILE_XAW">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
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</file>
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</file>
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<file xil_pn:name="init_ch7301c.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="init_ch7301c.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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</file>
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</file>
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<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
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<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</file>
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<file xil_pn:name="keyboard.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="keyboard.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="153"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="153"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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</file>
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</file>
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<file xil_pn:name="ps2.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="ps2.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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</file>
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<file xil_pn:name="font_rom.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="155"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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</file>
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</file>
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<file xil_pn:name="terminal_buffer.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="terminal_buffer.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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</file>
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<file xil_pn:name="terminal.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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</file>
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<file xil_pn:name="framebuffer.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="157"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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</file>
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</files>
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</files>
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<properties>
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<properties>
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@ -7,7 +7,7 @@ use ieee.numeric_std.all;
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use std.textio.all;
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use std.textio.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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entity font_rom is
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entity framebuffer is
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generic (
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generic (
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input_clk: integer
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input_clk: integer
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);
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);
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@ -18,9 +18,9 @@ entity font_rom is
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rgb: out std_logic_vector(23 downto 0)
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rgb: out std_logic_vector(23 downto 0)
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);
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);
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end font_rom;
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end framebuffer;
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architecture logic of font_rom is
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architecture logic of framebuffer is
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type rom_type is array(0 to 127) of std_logic_vector(63 downto 0);
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type rom_type is array(0 to 127) of std_logic_vector(63 downto 0);
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impure function read_font(filename: in string) return rom_type is
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impure function read_font(filename: in string) return rom_type is
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86
main.vhd
86
main.vhd
@ -1,11 +1,8 @@
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library ieee;
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library ieee;
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library unisim;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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-- Xilinx primitives (obufds)
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use unisim.VComponents.all;
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entity main is
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entity main is
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port (
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port (
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@ -29,88 +26,53 @@ entity main is
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rotary_down: in std_logic;
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rotary_down: in std_logic;
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rotary_push: in std_logic;
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rotary_push: in std_logic;
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led: out std_logic_vector(7 downto 0);
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led: out std_logic_vector(7 downto 0)
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led0: out std_logic;
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led1: out std_logic;
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led2: out std_logic;
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led4: out std_logic
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);
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);
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end main;
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end main;
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architecture Behavioral of main is
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architecture syn of main is
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constant clk_vga_f: integer := 48_000_000;
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signal clk_vga: std_logic;
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signal clk_vga: std_logic;
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signal image_x: std_logic_vector(9 downto 0);
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signal image_y: std_logic_vector(8 downto 0);
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signal reset: std_logic;
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signal pixel_rgb: std_logic_vector(23 downto 0);
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signal dvi_clk: std_logic; -- connect vga_sync to dvi_clk_ds
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-- tmp
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signal hsync: std_logic;
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signal vsync: std_logic;
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signal de: std_logic;
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begin
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begin
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reset <= switch_center;
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-- convert the 100MHz to a 48MHz pixel clock
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-- convert the 100MHz to a 48MHz pixel clock
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clock_source: entity work.clock_source port map (
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clock_source: entity work.clock_source port map (
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CLKIN_IN => clk,
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CLKIN_IN => clk,
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CLKFX_OUT => clk_vga
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CLKFX_OUT => clk_vga
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);
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);
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dvi_clk_ds: obufds port map (
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terminal: entity work.terminal generic map (
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O => dvi_clk_p,
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clk_f => clk_vga_f
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OB => dvi_clk_n,
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I => clk_vga
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);
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ch7301c: entity work.init_ch7301c generic map (
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input_clk => 48_000_000
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) port map (
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) port map (
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clk => clk_vga,
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clk => clk_vga,
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reset => switch_center,
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reset => reset,
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finished => open,
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error => open,
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i2c_scl => i2c_scl,
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i2c_sda => i2c_sda,
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dvi_reset => dvi_reset
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);
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vga_sync: entity work.vga port map (
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clk => clk_vga,
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x => image_x,
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y => image_y,
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pixel_rgb => pixel_rgb,
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dvi_d => dvi_d,
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dvi_d => dvi_d,
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dvi_clk => dvi_clk,
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dvi_clk_p => dvi_clk_p,
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dvi_hsync => hsync,
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dvi_clk_n => dvi_clk_n,
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dvi_vsync => vsync,
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dvi_hsync => dvi_hsync,
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dvi_de => de
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dvi_vsync => dvi_vsync,
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);
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dvi_de => dvi_de,
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dvi_reset => dvi_reset,
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framebuffer: entity work.font_rom generic map (
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i2c_scl => i2c_scl,
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input_clk => 48_000_000
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i2c_sda => i2c_sda
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) port map (
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clk => clk_vga,
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x => image_x,
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y => image_y,
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rgb => pixel_rgb
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);
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);
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keyboard_i: entity work.keyboard generic map (
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keyboard_i: entity work.keyboard generic map (
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input_clk => 48_000_000
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input_clk => clk_vga_f
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) port map (
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) port map (
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clk => clk_vga,
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clk => clk_vga,
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reset => switch_center,
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reset => reset,
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bytes_received => led(5 downto 0),
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bytes_received => led(5 downto 0),
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ps2_scl => ps2_scl,
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ps2_scl => ps2_scl,
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ps2_sda => ps2_sda
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ps2_sda => ps2_sda
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);
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);
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dvi_hsync <= hsync;
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led(7) <= reset;
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dvi_vsync <= vsync;
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dvi_de <= de;
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led(7) <= switch_center;
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led(6) <= '0';
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led(6) <= '0';
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--led1 <= dvi_clk;
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--led2 <= hsync;
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end syn;
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--led4 <= vsync;
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end Behavioral;
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75
terminal.vhd
Normal file
75
terminal.vhd
Normal file
@ -0,0 +1,75 @@
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library ieee;
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library unisim;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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-- Xilinx primitives (obufds)
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use unisim.VComponents.all;
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entity terminal is
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generic (
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clk_f: integer
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);
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port (
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clk: in std_logic;
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reset: in std_logic;
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dvi_d: out std_logic_vector(11 downto 0);
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dvi_clk_p: out std_logic;
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dvi_clk_n: out std_logic;
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dvi_hsync: out std_logic;
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dvi_vsync: out std_logic;
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dvi_de: out std_logic;
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dvi_reset: out std_logic;
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i2c_scl: inout std_logic;
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i2c_sda: inout std_logic
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);
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end terminal;
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architecture syn of terminal is
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signal image_x: std_logic_vector(9 downto 0);
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signal image_y: std_logic_vector(8 downto 0);
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signal pixel_rgb: std_logic_vector(23 downto 0);
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begin
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dvi_clk_ds: obufds port map (
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I => clk,
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O => dvi_clk_p,
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OB => dvi_clk_n
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);
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init_ch7301c: entity work.init_ch7301c generic map (
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input_clk => clk_f
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) port map (
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clk => clk,
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reset => reset,
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finished => open,
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error => open,
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i2c_scl => i2c_scl,
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i2c_sda => i2c_sda,
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dvi_reset => dvi_reset
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);
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vga: entity work.vga port map (
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clk => clk,
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x => image_x,
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y => image_y,
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pixel_rgb => pixel_rgb,
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dvi_d => dvi_d,
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dvi_hsync => dvi_hsync,
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dvi_vsync => dvi_vsync,
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dvi_de => dvi_de
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);
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framebuffer: entity work.framebuffer generic map (
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input_clk => clk_f
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) port map (
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clk => clk,
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x => image_x,
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y => image_y,
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rgb => pixel_rgb
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);
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end syn;
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3
vga.vhd
3
vga.vhd
@ -12,7 +12,6 @@ entity vga is
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pixel_rgb: in std_logic_vector(23 downto 0);
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pixel_rgb: in std_logic_vector(23 downto 0);
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dvi_d: out std_logic_vector(11 downto 0);
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dvi_d: out std_logic_vector(11 downto 0);
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dvi_clk: out std_logic;
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dvi_hsync: out std_logic;
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dvi_hsync: out std_logic;
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dvi_vsync: out std_logic;
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dvi_vsync: out std_logic;
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dvi_de: out std_logic
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dvi_de: out std_logic
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@ -25,8 +24,6 @@ architecture behavioral of vga is
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signal vcount: std_logic_vector(8 downto 0) := (others => '0');
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signal vcount: std_logic_vector(8 downto 0) := (others => '0');
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signal data_enabled: std_logic;
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signal data_enabled: std_logic;
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begin
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begin
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dvi_clk <= clk;
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--dvi_clk <= second_batch;
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dvi_de <= data_enabled;
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dvi_de <= data_enabled;
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data_enabled <= '1' when hcount < 640 and vcount < 480 else
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data_enabled <= '1' when hcount < 640 and vcount < 480 else
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