From 0aad663c337a786a20c47dc1dac94f66d9d94335 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= Date: Tue, 24 Apr 2018 21:58:42 +0200 Subject: [PATCH] Move vga and image creation entities into a new terminal entity --- dvi_test.xise | 26 +++++----- font_rom.vhd => framebuffer.vhd | 6 +-- main.vhd | 86 +++++++++------------------------ terminal.vhd | 75 ++++++++++++++++++++++++++++ vga.vhd | 3 -- 5 files changed, 117 insertions(+), 79 deletions(-) rename font_rom.vhd => framebuffer.vhd (97%) create mode 100644 terminal.vhd diff --git a/dvi_test.xise b/dvi_test.xise index 99cc276..9248ea9 100644 --- a/dvi_test.xise +++ b/dvi_test.xise @@ -17,7 +17,7 @@ - + @@ -27,39 +27,43 @@ - + - + - + - + - + - - - - - + + + + + + + + + diff --git a/font_rom.vhd b/framebuffer.vhd similarity index 97% rename from font_rom.vhd rename to framebuffer.vhd index 3ba5a50..ec27221 100644 --- a/font_rom.vhd +++ b/framebuffer.vhd @@ -7,7 +7,7 @@ use ieee.numeric_std.all; use std.textio.all; use ieee.std_logic_textio.all; -entity font_rom is +entity framebuffer is generic ( input_clk: integer ); @@ -18,9 +18,9 @@ entity font_rom is rgb: out std_logic_vector(23 downto 0) ); -end font_rom; +end framebuffer; -architecture logic of font_rom is +architecture logic of framebuffer is type rom_type is array(0 to 127) of std_logic_vector(63 downto 0); impure function read_font(filename: in string) return rom_type is diff --git a/main.vhd b/main.vhd index 4fa49b0..20adefe 100644 --- a/main.vhd +++ b/main.vhd @@ -1,11 +1,8 @@ library ieee; -library unisim; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; --- Xilinx primitives (obufds) -use unisim.VComponents.all; entity main is port ( @@ -29,88 +26,53 @@ entity main is rotary_down: in std_logic; rotary_push: in std_logic; - led: out std_logic_vector(7 downto 0); - - led0: out std_logic; - led1: out std_logic; - led2: out std_logic; - led4: out std_logic + led: out std_logic_vector(7 downto 0) ); end main; -architecture Behavioral of main is +architecture syn of main is + constant clk_vga_f: integer := 48_000_000; signal clk_vga: std_logic; - signal image_x: std_logic_vector(9 downto 0); - signal image_y: std_logic_vector(8 downto 0); - signal pixel_rgb: std_logic_vector(23 downto 0); - signal dvi_clk: std_logic; -- connect vga_sync to dvi_clk_ds - -- tmp - signal hsync: std_logic; - signal vsync: std_logic; - signal de: std_logic; + + signal reset: std_logic; begin + + reset <= switch_center; + -- convert the 100MHz to a 48MHz pixel clock clock_source: entity work.clock_source port map ( CLKIN_IN => clk, CLKFX_OUT => clk_vga ); - dvi_clk_ds: obufds port map ( - O => dvi_clk_p, - OB => dvi_clk_n, - I => clk_vga - ); - - ch7301c: entity work.init_ch7301c generic map ( - input_clk => 48_000_000 + terminal: entity work.terminal generic map ( + clk_f => clk_vga_f ) port map ( clk => clk_vga, - reset => switch_center, - finished => open, - error => open, - i2c_scl => i2c_scl, - i2c_sda => i2c_sda, - dvi_reset => dvi_reset - ); + reset => reset, - vga_sync: entity work.vga port map ( - clk => clk_vga, - x => image_x, - y => image_y, - pixel_rgb => pixel_rgb, dvi_d => dvi_d, - dvi_clk => dvi_clk, - dvi_hsync => hsync, - dvi_vsync => vsync, - dvi_de => de - ); - - framebuffer: entity work.font_rom generic map ( - input_clk => 48_000_000 - ) port map ( - clk => clk_vga, - x => image_x, - y => image_y, - rgb => pixel_rgb + dvi_clk_p => dvi_clk_p, + dvi_clk_n => dvi_clk_n, + dvi_hsync => dvi_hsync, + dvi_vsync => dvi_vsync, + dvi_de => dvi_de, + dvi_reset => dvi_reset, + i2c_scl => i2c_scl, + i2c_sda => i2c_sda ); keyboard_i: entity work.keyboard generic map ( - input_clk => 48_000_000 + input_clk => clk_vga_f ) port map ( clk => clk_vga, - reset => switch_center, + reset => reset, bytes_received => led(5 downto 0), ps2_scl => ps2_scl, ps2_sda => ps2_sda ); - dvi_hsync <= hsync; - dvi_vsync <= vsync; - dvi_de <= de; - - led(7) <= switch_center; + led(7) <= reset; led(6) <= '0'; - --led1 <= dvi_clk; - --led2 <= hsync; - --led4 <= vsync; -end Behavioral; + +end syn; diff --git a/terminal.vhd b/terminal.vhd new file mode 100644 index 0000000..cce3058 --- /dev/null +++ b/terminal.vhd @@ -0,0 +1,75 @@ +library ieee; +library unisim; + +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +-- Xilinx primitives (obufds) +use unisim.VComponents.all; + +entity terminal is + generic ( + clk_f: integer + ); + port ( + clk: in std_logic; + reset: in std_logic; + + dvi_d: out std_logic_vector(11 downto 0); + dvi_clk_p: out std_logic; + dvi_clk_n: out std_logic; + dvi_hsync: out std_logic; + dvi_vsync: out std_logic; + dvi_de: out std_logic; + dvi_reset: out std_logic; + i2c_scl: inout std_logic; + i2c_sda: inout std_logic + ); +end terminal; + +architecture syn of terminal is + signal image_x: std_logic_vector(9 downto 0); + signal image_y: std_logic_vector(8 downto 0); + signal pixel_rgb: std_logic_vector(23 downto 0); +begin + + dvi_clk_ds: obufds port map ( + I => clk, + O => dvi_clk_p, + OB => dvi_clk_n + ); + + init_ch7301c: entity work.init_ch7301c generic map ( + input_clk => clk_f + ) port map ( + clk => clk, + reset => reset, + finished => open, + error => open, + i2c_scl => i2c_scl, + i2c_sda => i2c_sda, + dvi_reset => dvi_reset + ); + + vga: entity work.vga port map ( + clk => clk, + x => image_x, + y => image_y, + pixel_rgb => pixel_rgb, + dvi_d => dvi_d, + dvi_hsync => dvi_hsync, + dvi_vsync => dvi_vsync, + dvi_de => dvi_de + ); + + framebuffer: entity work.framebuffer generic map ( + input_clk => clk_f + ) port map ( + clk => clk, + x => image_x, + y => image_y, + rgb => pixel_rgb + ); + +end syn; + diff --git a/vga.vhd b/vga.vhd index 8ccdc76..08d8889 100644 --- a/vga.vhd +++ b/vga.vhd @@ -12,7 +12,6 @@ entity vga is pixel_rgb: in std_logic_vector(23 downto 0); dvi_d: out std_logic_vector(11 downto 0); - dvi_clk: out std_logic; dvi_hsync: out std_logic; dvi_vsync: out std_logic; dvi_de: out std_logic @@ -25,8 +24,6 @@ architecture behavioral of vga is signal vcount: std_logic_vector(8 downto 0) := (others => '0'); signal data_enabled: std_logic; begin - dvi_clk <= clk; - --dvi_clk <= second_batch; dvi_de <= data_enabled; data_enabled <= '1' when hcount < 640 and vcount < 480 else