Move vga and image creation entities into a new terminal entity

terminal.vhd

@@ -0,0 +1,75 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+-- Xilinx primitives (obufds)
+use unisim.VComponents.all;
+
+entity terminal is
+    generic (
+        clk_f: integer
+    );
+    port (
+        clk: in std_logic;
+        reset: in std_logic;
+
+        dvi_d: out std_logic_vector(11 downto 0);
+        dvi_clk_p: out std_logic;
+        dvi_clk_n: out std_logic;
+        dvi_hsync: out std_logic;
+        dvi_vsync: out std_logic;
+        dvi_de: out std_logic;
+        dvi_reset: out std_logic;
+        i2c_scl: inout std_logic;
+        i2c_sda: inout std_logic
+    );
+end terminal;
+
+architecture syn of terminal is
+    signal image_x: std_logic_vector(9 downto 0);
+    signal image_y: std_logic_vector(8 downto 0);
+    signal pixel_rgb: std_logic_vector(23 downto 0);
+begin
+
+    dvi_clk_ds: obufds port map (
+        I => clk,
+        O => dvi_clk_p,
+        OB => dvi_clk_n
+    );
+
+    init_ch7301c: entity work.init_ch7301c generic map (
+        input_clk => clk_f
+    ) port map (
+        clk => clk,
+        reset => reset,
+        finished => open,
+        error => open,
+        i2c_scl => i2c_scl,
+        i2c_sda => i2c_sda,
+        dvi_reset => dvi_reset
+    );
+
+    vga: entity work.vga port map (
+        clk => clk,
+        x => image_x,
+        y => image_y,
+        pixel_rgb => pixel_rgb,
+        dvi_d => dvi_d,
+        dvi_hsync => dvi_hsync,
+        dvi_vsync => dvi_vsync,
+        dvi_de => dvi_de
+    );
+
+    framebuffer: entity work.framebuffer generic map (
+        input_clk => clk_f
+    ) port map (
+        clk => clk,
+        x => image_x,
+        y => image_y,
+        rgb => pixel_rgb
+    );
+
+end syn;
+