terminal/vga_test.vhd

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:47:34 11/01/2017
-- Design Name:
-- Module Name: /repos/master/dvi_test/vga_test.vhd
-- Project Name: dvi_test
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: vga
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY vga_test IS
END vga_test;
ARCHITECTURE behavior OF vga_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT vga
PORT(
clk : IN std_logic;
--x : OUT std_logic_vector(9 downto 0);
--y : OUT std_logic_vector(9 downto 0);
--pixel_rgb : IN std_logic_vector(23 downto 0);
dvi_d : OUT std_logic_vector(11 downto 0);
--dvi_clk : OUT std_logic;
dvi_clk_p : OUT std_logic;
dvi_clk_n : OUT std_logic;
dvi_hsync : OUT std_logic;
dvi_vsync : OUT std_logic;
dvi_de : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--signal pixel_rgb : std_logic_vector(23 downto 0) := (others => '0');
--Outputs
--signal x : std_logic_vector(9 downto 0);
--signal y : std_logic_vector(9 downto 0);
signal dvi_d : std_logic_vector(11 downto 0);
--signal dvi_clk : std_logic;
signal dvi_clk_p : std_logic;
signal dvi_clk_n : std_logic;
signal dvi_hsync : std_logic;
signal dvi_vsync : std_logic;
signal dvi_de : std_logic;
-- Clock period definitions
constant clk_period : time := 20834 ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: vga PORT MAP (
clk => clk,
--x => x,
--y => y,
--pixel_rgb => pixel_rgb,
dvi_d => dvi_d,
--dvi_clk => dvi_clk,
dvi_clk_p => dvi_clk_p,
dvi_clk_n => dvi_clk_n,
dvi_hsync => dvi_hsync,
dvi_vsync => dvi_vsync,
dvi_de => dvi_de
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
--pixel_rgb <= "111111111111000000000001";
END;