terminal/clock_source.vhd

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-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : clock_source.vhd
-- /___/ /\ Timestamp : 11/13/2017 01:32:13
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /repos/master/dvi_test/ipcore_dir/clock_source.xaw -st clock_source.vhd
--Design Name: clock_source
--Device: xc5vfx70t-ff1136-3
--
-- Module clock_source
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_ADV_INST = 0.024 UI
-- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.502 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity clock_source is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic);
end clock_source;
architecture BEHAVIORAL of clock_source is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
signal GND_BUS_7 : std_logic_vector (6 downto 0);
signal GND_BUS_16 : std_logic_vector (15 downto 0);
begin
GND_BIT <= '0';
GND_BUS_7(6 downto 0) <= "0000000";
GND_BUS_16(15 downto 0) <= "0000000000000000";
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_ADV_INST : DCM_ADV
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 25,
CLKFX_MULTIPLY => 12,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.000,
CLKOUT_PHASE_SHIFT => "NONE",
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE,
SIM_DEVICE => "VIRTEX5")
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DADDR(6 downto 0)=>GND_BUS_7(6 downto 0),
DCLK=>GND_BIT,
DEN=>GND_BIT,
DI(15 downto 0)=>GND_BUS_16(15 downto 0),
DWE=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
DO=>open,
DRDY=>open,
LOCKED=>open,
PSDONE=>open);
end BEHAVIORAL;