107 lines
3.7 KiB
Scala
107 lines
3.7 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.util
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import Chisel._
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import Chisel.ImplicitConversions._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.util.WideCounter
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class SlaveRegIF(w: Int) extends Bundle {
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val write = Valid(UInt(width = w)).flip
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val read = UInt(OUTPUT, w)
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override def cloneType: this.type = new SlaveRegIF(w).asInstanceOf[this.type]
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def toRegField(dummy: Int = 0): RegField = {
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def writeFn(valid: Bool, data: UInt): Bool = {
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write.valid := valid
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write.bits := data
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Bool(true)
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}
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RegField(w, RegReadFn(read), RegWriteFn((v, d) => writeFn(v, d)))
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}
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}
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abstract class GenericTimer extends Module {
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protected def countWidth: Int
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protected def cmpWidth: Int
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protected def ncmp: Int
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protected def countAlways: Bool
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protected def countEn: Bool
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protected def feed: Bool
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protected def ip: UInt
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protected def countAwake: Bool = Bool(false)
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protected def unlocked: Bool = Bool(true)
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protected def rsten: Bool = Bool(false)
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protected def deglitch: Bool = Bool(false)
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protected def sticky: Bool = Bool(false)
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protected def oneShot: Bool = Bool(false)
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protected def center: UInt = UInt(0)
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protected def extra: UInt = UInt(0)
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protected def gang: UInt = UInt(0)
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protected val scaleWidth = 4
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protected val regWidth = 32
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val maxcmp = 4
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require(ncmp <= maxcmp)
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class GenericTimerIO extends Bundle {
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val regs = new Bundle {
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val cfg = new SlaveRegIF(regWidth)
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val countLo = new SlaveRegIF(regWidth)
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val countHi = new SlaveRegIF(regWidth)
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val s = new SlaveRegIF(cmpWidth)
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val cmp = Vec(ncmp, new SlaveRegIF(cmpWidth))
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val feed = new SlaveRegIF(regWidth)
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val key = new SlaveRegIF(regWidth)
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}
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val ip = Vec(ncmp, Bool()).asOutput
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}
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def io: GenericTimerIO
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protected val scale = RegEnable(io.regs.cfg.write.bits(scaleWidth-1, 0), io.regs.cfg.write.valid && unlocked)
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protected lazy val zerocmp = RegEnable(io.regs.cfg.write.bits(9), io.regs.cfg.write.valid && unlocked)
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protected val cmp = io.regs.cmp.map(c => RegEnable(c.write.bits, c.write.valid && unlocked))
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protected val count = WideCounter(countWidth, countEn, reset = false)
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when (io.regs.countLo.write.valid && unlocked) { count := Cat(count >> regWidth, io.regs.countLo.write.bits) }
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if (countWidth > regWidth) when (io.regs.countHi.write.valid && unlocked) { count := Cat(io.regs.countHi.write.bits, count(regWidth-1, 0)) }
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// generate periodic interrupt
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protected val s = (count >> scale)(cmpWidth-1, 0)
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// reset counter when fed or elapsed
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protected val elapsed =
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for (i <- 0 until ncmp)
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yield Mux(s(cmpWidth-1) && center(i), ~s, s) >= cmp(i)
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protected val countReset = feed || (zerocmp && elapsed(0))
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when (countReset) { count := 0 }
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io.regs.cfg.read := Cat(ip, gang | UInt(0, maxcmp), extra | UInt(0, maxcmp), center | UInt(0, maxcmp),
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UInt(0, 2), countAwake || oneShot, countAlways, UInt(0, 1), deglitch, zerocmp, rsten || sticky,
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UInt(0, 8-scaleWidth), scale)
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io.regs.countLo.read := count
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io.regs.countHi.read := count >> regWidth
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io.regs.s.read := s
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(io.regs.cmp zip cmp) map { case (r, c) => r.read := c }
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io.regs.feed.read := 0
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io.regs.key.read := unlocked
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io.ip := io.ip.fromBits(ip)
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}
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object GenericTimer {
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def timerRegMap(t: GenericTimer, offset: Int, regBytes: Int): Seq[(Int, Seq[RegField])] = {
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val regs = Seq(
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0 -> t.io.regs.cfg,
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2 -> t.io.regs.countLo,
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3 -> t.io.regs.countHi,
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4 -> t.io.regs.s,
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6 -> t.io.regs.feed,
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7 -> t.io.regs.key)
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val cmpRegs = t.io.regs.cmp.zipWithIndex map { case (r, i) => (8 + i) -> r }
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for ((i, r) <- (regs ++ cmpRegs))
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yield (offset + regBytes*i) -> Seq(r.toRegField())
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}
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}
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