35 lines
1018 B
Scala
35 lines
1018 B
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.gpio
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import Chisel._
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import config.Field
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import diplomacy.{LazyModule,LazyMultiIOModuleImp}
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import rocketchip.HasSystemNetworks
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import uncore.tilelink2.TLFragmenter
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import util.HeterogeneousBag
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case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
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trait HasPeripheryGPIO extends HasSystemNetworks {
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val gpioParams = p(PeripheryGPIOKey)
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val gpio = gpioParams map {params =>
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val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
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gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := gpio.intnode
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gpio
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}
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}
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trait HasPeripheryGPIOBundle {
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val gpio: HeterogeneousBag[GPIOPortIO]
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}
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trait HasPeripheryGPIOModuleImp extends LazyMultiIOModuleImp with HasPeripheryGPIOBundle {
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val outer: HasPeripheryGPIO
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val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
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(gpio zip outer.gpio) foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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