31 lines
938 B
Scala
31 lines
938 B
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.xilinxvc707mig
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import Chisel._
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import freechips.rocketchip.coreplex.HasMemoryBus
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import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
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trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
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val module: HasMemoryXilinxVC707MIGModuleImp
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val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
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require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
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xilinxvc707mig.node := memBuses.head.toDRAMController
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}
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trait HasMemoryXilinxVC707MIGBundle {
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val xilinxvc707mig: XilinxVC707MIGIO
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def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
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pads <> xilinxvc707mig
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}
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}
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trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
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with HasMemoryXilinxVC707MIGBundle {
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val outer: HasMemoryXilinxVC707MIG
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val xilinxvc707mig = IO(new XilinxVC707MIGIO)
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xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
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}
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