43 lines
1.0 KiB
Scala
43 lines
1.0 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.util
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import Chisel._
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import util.AsyncResetRegVec
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/** Reset: asynchronous assert,
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* synchronous de-assert
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*
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*/
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class ResetCatchAndSync (sync: Int = 3) extends Module {
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val io = new Bundle {
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val sync_reset = Bool(OUTPUT)
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}
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val reset_n_catch_reg = Module (new AsyncResetRegVec(sync, 0))
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reset_n_catch_reg.io.en := Bool(true)
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reset_n_catch_reg.io.d := Cat(Bool(true), reset_n_catch_reg.io.q >> 1)
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io.sync_reset := ~reset_n_catch_reg.io.q(0)
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}
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object ResetCatchAndSync {
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def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None): Bool = {
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val catcher = Module (new ResetCatchAndSync(sync))
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if (name.isDefined) {catcher.suggestName(name.get)}
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catcher.clock := clk
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catcher.reset := rst
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catcher.io.sync_reset
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}
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def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
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def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
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}
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