29 lines
760 B
Scala
29 lines
760 B
Scala
// See LICENSE for license details.
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package sifive.blocks.util
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import Chisel._
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//Allows us to specify a different clock for a shift register
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// and to force input to be high for > 1 cycle.
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class DeglitchShiftRegister(shift: Int) extends Module {
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val io = new Bundle {
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val d = Bool(INPUT)
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val q = Bool(OUTPUT)
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}
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val sync = ShiftRegister(io.d, shift)
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val last = ShiftRegister(sync, 1)
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io.q := sync & last
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}
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object DeglitchShiftRegister {
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def apply (shift: Int, d: Bool, clock: Clock,
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name: Option[String] = None): Bool = {
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val deglitch = Module (new DeglitchShiftRegister(shift))
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name.foreach(deglitch.suggestName(_))
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deglitch.clock := clock
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deglitch.reset := Bool(false)
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deglitch.io.d := d
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deglitch.io.q
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}
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}
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