111 lines
4.2 KiB
Scala
111 lines
4.2 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.ip.xilinx.vc707mig
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import Chisel._
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import config._
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import junctions._
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// IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
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// Black Box
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// Signals named _exactly_ as per MIG generated verilog
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trait VC707MIGUnidirectionalIODDR extends Bundle {
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//outputs
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val ddr3_addr = Bits(OUTPUT,14)
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val ddr3_ba = Bits(OUTPUT,3)
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val ddr3_ras_n = Bool(OUTPUT)
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val ddr3_cas_n = Bool(OUTPUT)
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val ddr3_we_n = Bool(OUTPUT)
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val ddr3_reset_n = Bool(OUTPUT)
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val ddr3_ck_p = Bits(OUTPUT,1)
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val ddr3_ck_n = Bits(OUTPUT,1)
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val ddr3_cke = Bits(OUTPUT,1)
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val ddr3_cs_n = Bits(OUTPUT,1)
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val ddr3_dm = Bits(OUTPUT,8)
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val ddr3_odt = Bits(OUTPUT,1)
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}
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//reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
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trait VC707MIGUnidirectionalIOClocksReset extends Bundle {
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//inputs
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//differential system clocks
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val sys_clk_n = Bool(INPUT)
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val sys_clk_p = Bool(INPUT)
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//user interface signals
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val ui_clk = Clock(OUTPUT)
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val ui_clk_sync_rst = Bool(OUTPUT)
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val mmcm_locked = Bool(OUTPUT)
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val aresetn = Bool(INPUT)
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//misc
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val init_calib_complete = Bool(OUTPUT)
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val sys_rst = Bool(INPUT)
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}
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//scalastyle:off
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//turn off linter: blackbox name must match verilog module
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class vc707mig(implicit val p:Parameters) extends BlackBox
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{
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val io = new Bundle with VC707MIGUnidirectionalIODDR
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with VC707MIGUnidirectionalIOClocksReset {
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// bidirectional signals on blackbox interface
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// defined here as an output so "__inout" signal name does not have to be used
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// verilog does not check the
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val ddr3_dq = Bits(OUTPUT,64)
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val ddr3_dqs_n = Bits(OUTPUT,8)
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val ddr3_dqs_p = Bits(OUTPUT,8)
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// User interface signals
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val app_sr_req = Bool(INPUT)
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val app_ref_req = Bool(INPUT)
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val app_zq_req = Bool(INPUT)
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val app_sr_active = Bool(OUTPUT)
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val app_ref_ack = Bool(OUTPUT)
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val app_zq_ack = Bool(OUTPUT)
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//axi_s
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//slave interface write address ports
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val s_axi_awid = Bits(INPUT,4)
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val s_axi_awaddr = Bits(INPUT,30)
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val s_axi_awlen = Bits(INPUT,8)
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val s_axi_awsize = Bits(INPUT,3)
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val s_axi_awburst = Bits(INPUT,2)
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val s_axi_awlock = Bits(INPUT,1)
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val s_axi_awcache = Bits(INPUT,4)
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val s_axi_awprot = Bits(INPUT,3)
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val s_axi_awqos = Bits(INPUT,4)
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val s_axi_awvalid = Bool(INPUT)
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val s_axi_awready = Bool(OUTPUT)
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//slave interface write data ports
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val s_axi_wdata = Bits(INPUT,64)
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val s_axi_wstrb = Bits(INPUT,8)
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val s_axi_wlast = Bool(INPUT)
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val s_axi_wvalid = Bool(INPUT)
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val s_axi_wready = Bool(OUTPUT)
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//slave interface write response ports
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val s_axi_bready = Bool(INPUT)
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val s_axi_bid = Bits(OUTPUT,4)
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val s_axi_bresp = Bits(OUTPUT,2)
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val s_axi_bvalid = Bool(OUTPUT)
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//slave interface read address ports
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val s_axi_arid = Bits(INPUT,4)
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val s_axi_araddr = Bits(INPUT,30)
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val s_axi_arlen = Bits(INPUT,8)
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val s_axi_arsize = Bits(INPUT,3)
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val s_axi_arburst = Bits(INPUT,2)
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val s_axi_arlock = Bits(INPUT,1)
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val s_axi_arcache = Bits(INPUT,4)
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val s_axi_arprot = Bits(INPUT,3)
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val s_axi_arqos = Bits(INPUT,4)
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val s_axi_arvalid = Bool(INPUT)
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val s_axi_arready = Bool(OUTPUT)
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//slave interface read data ports
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val s_axi_rready = Bool(INPUT)
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val s_axi_rid = Bits(OUTPUT,4)
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val s_axi_rdata = Bits(OUTPUT,64)
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val s_axi_rresp = Bits(OUTPUT,2)
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val s_axi_rlast = Bool(OUTPUT)
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val s_axi_rvalid = Bool(OUTPUT)
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//misc
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val device_temp = Bits(OUTPUT,12)
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}
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}
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//scalastyle:on
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