276 lines
7.2 KiB
Scala
276 lines
7.2 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.uart
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import Chisel._
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import config._
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import regmapper._
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import uncore.tilelink2._
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import junctions._
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import util._
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import rocketchip.PeripheryBusConfig
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import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
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case class UARTConfig(
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address: BigInt,
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dataBits: Int = 8,
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stopBits: Int = 2,
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divisorBits: Int = 16,
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oversample: Int = 4,
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nSamples: Int = 3,
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nTxEntries: Int = 8,
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nRxEntries: Int = 8)
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trait HasUARTParameters {
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val c: UARTConfig
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val uartDataBits = c.dataBits
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val uartStopBits = c.stopBits
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val uartDivisorBits = c.divisorBits
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val uartOversample = c.oversample
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val uartOversampleFactor = 1 << uartOversample
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val uartNSamples = c.nSamples
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val uartNTxEntries = c.nTxEntries
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val uartNRxEntries = c.nRxEntries
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require(uartDivisorBits > uartOversample)
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require(uartOversampleFactor > uartNSamples)
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}
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abstract class UARTModule(val c: UARTConfig)(implicit val p: Parameters)
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extends Module with HasUARTParameters
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class UARTPortIO extends Bundle {
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val txd = Bool(OUTPUT)
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val rxd = Bool(INPUT)
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}
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trait MixUARTParameters {
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val params: (UARTConfig, Parameters)
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val c = params._1
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implicit val p = params._2
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}
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trait UARTTopBundle extends Bundle with MixUARTParameters with HasUARTParameters {
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val port = new UARTPortIO
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}
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class UARTTx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
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val io = new Bundle {
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val en = Bool(INPUT)
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val in = Decoupled(Bits(width = uartDataBits)).flip
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val out = Bits(OUTPUT, 1)
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val div = UInt(INPUT, uartDivisorBits)
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val nstop = UInt(INPUT, log2Up(uartStopBits))
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}
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val prescaler = Reg(init = UInt(0, uartDivisorBits))
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val pulse = (prescaler === UInt(0))
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private val n = uartDataBits + 1
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val counter = Reg(init = UInt(0, log2Floor(n + uartStopBits) + 1))
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val shifter = Reg(Bits(width = n))
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val out = Reg(init = Bits(1, 1))
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io.out := out
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val busy = (counter =/= UInt(0))
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io.in.ready := io.en && !busy
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when (io.in.fire()) {
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printf("%c", io.in.bits)
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shifter := Cat(io.in.bits, Bits(0, 1))
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counter := Mux1H((0 until uartStopBits).map(i =>
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(io.nstop === UInt(i)) -> UInt(n + i + 1)))
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}
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when (busy) {
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prescaler := Mux(pulse, io.div, prescaler - UInt(1))
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}
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when (pulse && busy) {
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counter := counter - UInt(1)
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shifter := Cat(Bits(1, 1), shifter >> 1)
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out := shifter(0)
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}
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}
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class UARTRx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
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val io = new Bundle {
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val en = Bool(INPUT)
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val in = Bits(INPUT, 1)
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val out = Valid(Bits(width = uartDataBits))
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val div = UInt(INPUT, uartDivisorBits)
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}
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val debounce = Reg(init = UInt(0, 2))
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val debounce_max = (debounce === UInt(3))
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val debounce_min = (debounce === UInt(0))
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val prescaler = Reg(init = UInt(0, uartDivisorBits - uartOversample))
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val start = Wire(init = Bool(false))
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val busy = Wire(init = Bool(false))
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val pulse = (prescaler === UInt(0)) && busy
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when (busy) {
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prescaler := prescaler - UInt(1)
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}
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when (start || pulse) {
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prescaler := io.div >> uartOversample
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}
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val sample = Reg(Bits(width = uartNSamples))
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val voter = new Majority(sample.toBools.toSet)
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when (pulse) {
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sample := Cat(sample, io.in)
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}
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private val delay0 = (uartOversampleFactor + uartNSamples) >> 1
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private val delay1 = uartOversampleFactor
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val timer = Reg(UInt(width = uartOversample + 1))
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val counter = Reg(UInt(width = log2Floor(uartDataBits) + 1))
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val shifter = Reg(Bits(width = uartDataBits))
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val expire = (timer === UInt(0)) && pulse
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val sched = Wire(init = Bool(false))
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when (pulse) {
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timer := timer - UInt(1)
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}
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when (sched) {
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timer := UInt(delay1-1)
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}
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val valid = Reg(init = Bool(false))
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valid := Bool(false)
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io.out.valid := valid
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io.out.bits := shifter
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val (s_idle :: s_start :: s_data :: Nil) = Enum(UInt(), 3)
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val state = Reg(init = s_idle)
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switch (state) {
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is (s_idle) {
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when (!(!io.in) && !debounce_min) {
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debounce := debounce - UInt(1)
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}
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when (!io.in) {
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debounce := debounce + UInt(1)
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when (debounce_max) {
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state := s_start
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start := Bool(true)
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timer := UInt(delay0-1)
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}
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}
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}
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is (s_start) {
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busy := Bool(true)
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when (expire) {
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sched := Bool(true)
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when (voter.out) {
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state := s_idle
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} .otherwise {
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state := s_data
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counter := UInt(uartDataBits)
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}
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}
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}
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is (s_data) {
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busy := Bool(true)
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when (expire) {
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counter := counter - UInt(1)
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when (counter === UInt(0)) {
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state := s_idle
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valid := Bool(true)
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} .otherwise {
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shifter := Cat(voter.out, shifter >> 1)
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sched := Bool(true)
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}
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}
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}
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}
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when (!io.en) {
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debounce := UInt(0)
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}
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}
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class UARTInterrupts extends Bundle {
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val rxwm = Bool()
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val txwm = Bool()
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}
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trait UARTTopModule extends Module with MixUARTParameters with HasUARTParameters with HasRegMap {
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val io: UARTTopBundle
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val txm = Module(new UARTTx(c))
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val txq = Module(new Queue(txm.io.in.bits, uartNTxEntries))
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val rxm = Module(new UARTRx(c))
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val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
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val divinit = 542 // (62.5MHz / 115200)
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val div = Reg(init = UInt(divinit, uartDivisorBits))
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private val stopCountBits = log2Up(uartStopBits)
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private val txCountBits = log2Floor(uartNTxEntries) + 1
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private val rxCountBits = log2Floor(uartNRxEntries) + 1
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val txen = Reg(init = Bool(false))
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val rxen = Reg(init = Bool(false))
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val txwm = Reg(init = UInt(0, txCountBits))
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val rxwm = Reg(init = UInt(0, rxCountBits))
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val nstop = Reg(init = UInt(0, stopCountBits))
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txm.io.en := txen
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txm.io.in <> txq.io.deq
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txm.io.div := div
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txm.io.nstop := nstop
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io.port.txd := txm.io.out
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rxm.io.en := rxen
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rxm.io.in := io.port.rxd
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rxq.io.enq <> rxm.io.out
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rxm.io.div := div
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val ie = Reg(init = new UARTInterrupts().fromBits(Bits(0)))
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val ip = Wire(new UARTInterrupts)
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ip.txwm := (txq.io.count < txwm)
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ip.rxwm := (rxq.io.count > rxwm)
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interrupts(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
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regmap(
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UARTCtrlRegs.txfifo -> NonBlockingEnqueue(txq.io.enq),
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UARTCtrlRegs.rxfifo -> NonBlockingDequeue(rxq.io.deq),
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UARTCtrlRegs.txctrl -> Seq(
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RegField(1, txen),
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RegField(stopCountBits, nstop)),
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UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen)),
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UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm)),
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UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm)),
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UARTCtrlRegs.ie -> Seq(
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RegField(1, ie.txwm),
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RegField(1, ie.rxwm)),
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UARTCtrlRegs.ip -> Seq(
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RegField.r(1, ip.txwm),
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RegField.r(1, ip.rxwm)),
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UARTCtrlRegs.div -> Seq(
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RegField(uartDivisorBits, div))
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)
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}
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class Majority(in: Set[Bool]) {
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private val n = (in.size >> 1) + 1
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private val clauses = in.subsets(n).map(_.reduce(_ && _))
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val out = clauses.reduce(_ || _)
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}
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// Magic TL2 Incantation to create a TL2 Slave
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class UART(c: UARTConfig)(implicit val p: Parameters)
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extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = p(PeripheryBusConfig).beatBytes)(
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new TLRegBundle((c, p), _) with UARTTopBundle)(
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new TLRegModule((c, p), _, _) with UARTTopModule)
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