133 lines
3.8 KiB
Scala
133 lines
3.8 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.spi
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import Chisel._
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import config._
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import uncore.tilelink2._
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import diplomacy._
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import regmapper._
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import junctions._
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import rocketchip.PeripheryBusConfig
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import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
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trait SPIConfigBase {
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val rAddress: BigInt
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val rSize: BigInt
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val rxDepth: Int
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val txDepth: Int
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val csWidth: Int
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val frameBits: Int
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val delayBits: Int
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val divisorBits: Int
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val sampleDelay: Int
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lazy val csIdBits = log2Up(csWidth)
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lazy val lengthBits = log2Floor(frameBits) + 1
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lazy val countBits = math.max(lengthBits, delayBits)
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lazy val txDepthBits = log2Floor(txDepth) + 1
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lazy val rxDepthBits = log2Floor(rxDepth) + 1
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lazy val bc = new SPIBundleConfig(csWidth)
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}
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case class SPIConfig(
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rAddress: BigInt,
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rSize: BigInt = 0x1000,
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rxDepth: Int = 8,
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txDepth: Int = 8,
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csWidth: Int = 1,
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frameBits: Int = 8,
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delayBits: Int = 8,
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divisorBits: Int = 12,
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sampleDelay: Int = 2)
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extends SPIConfigBase {
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require(frameBits >= 4)
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require(sampleDelay >= 0)
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}
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case class SPIBundleConfig(csWidth: Int)
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{
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def union(that: SPIBundleConfig): SPIBundleConfig =
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SPIBundleConfig(scala.math.max(csWidth, that.csWidth))
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def toSPIConfig: SPIConfig = new SPIConfig(rAddress = -1,
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csWidth = csWidth)
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}
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class SPITopBundle(val i: Vec[Vec[Bool]], val r: Vec[TLBundle]) extends Bundle
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class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLSPIBase)
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extends LazyModuleImp(outer) {
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val io = new Bundle {
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val port = new SPIPortIO(c)
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val tl = bundle
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}
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val ctrl = Reg(init = SPIControl.init(c))
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val fifo = Module(new SPIFIFO(c))
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val mac = Module(new SPIMedia(c))
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io.port <> mac.io.port
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fifo.io.ctrl.fmt := ctrl.fmt
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fifo.io.ctrl.cs <> ctrl.cs
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fifo.io.ctrl.wm := ctrl.wm
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mac.io.ctrl.sck := ctrl.sck
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mac.io.ctrl.dla := ctrl.dla
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mac.io.ctrl.cs <> ctrl.cs
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val ie = Reg(init = new SPIInterrupts().fromBits(Bits(0)))
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val ip = fifo.io.ip
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io.tl.i(0)(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
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protected val regmapBase = Seq(
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SPICRs.sckdiv -> Seq(RegField(c.divisorBits, ctrl.sck.div)),
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SPICRs.sckmode -> Seq(
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RegField(1, ctrl.sck.pha),
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RegField(1, ctrl.sck.pol)),
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SPICRs.csid -> Seq(RegField(c.csIdBits, ctrl.cs.id)),
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SPICRs.csdef -> ctrl.cs.dflt.map(x => RegField(1, x)),
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SPICRs.csmode -> Seq(RegField(SPICSMode.width, ctrl.cs.mode)),
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SPICRs.dcssck -> Seq(RegField(c.delayBits, ctrl.dla.cssck)),
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SPICRs.dsckcs -> Seq(RegField(c.delayBits, ctrl.dla.sckcs)),
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SPICRs.dintercs -> Seq(RegField(c.delayBits, ctrl.dla.intercs)),
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SPICRs.dinterxfr -> Seq(RegField(c.delayBits, ctrl.dla.interxfr)),
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SPICRs.fmt -> Seq(
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RegField(SPIProtocol.width, ctrl.fmt.proto),
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RegField(SPIEndian.width, ctrl.fmt.endian),
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RegField(SPIDirection.width, ctrl.fmt.iodir)),
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SPICRs.len -> Seq(RegField(c.lengthBits, ctrl.fmt.len)),
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SPICRs.txfifo -> NonBlockingEnqueue(fifo.io.tx),
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SPICRs.rxfifo -> NonBlockingDequeue(fifo.io.rx),
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SPICRs.txmark -> Seq(RegField(c.txDepthBits, ctrl.wm.tx)),
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SPICRs.rxmark -> Seq(RegField(c.rxDepthBits, ctrl.wm.rx)),
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SPICRs.ie -> Seq(
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RegField(1, ie.txwm),
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RegField(1, ie.rxwm)),
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SPICRs.ip -> Seq(
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RegField.r(1, ip.txwm),
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RegField.r(1, ip.rxwm)))
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}
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abstract class TLSPIBase(c: SPIConfigBase)(implicit val p: Parameters) extends LazyModule {
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require(isPow2(c.rSize))
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val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), beatBytes = p(PeripheryBusConfig).beatBytes)
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val intnode = IntSourceNode(1)
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}
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class TLSPI(c: SPIConfig)(implicit p: Parameters) extends TLSPIBase(c)(p) {
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lazy val module = new SPITopModule(c, new SPITopBundle(intnode.bundleOut, rnode.bundleIn), this) {
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mac.io.link <> fifo.io.link
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rnode.regmap(regmapBase:_*)
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}
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}
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