35 lines
994 B
Scala
35 lines
994 B
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.spi
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import Chisel._
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import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
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class SPIPinsIO(c: SPIConfigBase) extends SPIBundle(c) {
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val sck = new GPIOPin
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val dq = Vec(4, new GPIOPin)
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val cs = Vec(c.csWidth, new GPIOPin)
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}
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class SPIGPIOPort(c: SPIConfigBase, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
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val io = new SPIBundle(c) {
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val spi = new SPIPortIO(c).flip
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val pins = new SPIPinsIO(c)
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}
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GPIOOutputPinCtrl(io.pins.sck, io.spi.sck, ds = driveStrength)
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GPIOOutputPinCtrl(io.pins.dq, Bits(0, io.spi.dq.size))
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(io.pins.dq zip io.spi.dq).foreach {
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case (p, s) =>
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p.o.oval := s.o
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p.o.oe := s.oe
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p.o.ie := ~s.oe
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p.o.pue := Bool(true)
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p.o.ds := driveStrength
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s.i := ShiftRegister(p.i.ival, syncStages)
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}
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GPIOOutputPinCtrl(io.pins.cs, io.spi.cs.asUInt)
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io.pins.cs.foreach(_.o.ds := driveStrength)
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}
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