58 lines
1.7 KiB
Scala
58 lines
1.7 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.spi
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import Chisel._
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import diplomacy.LazyModule
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import uncore.tilelink2._
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import rocketchip.{TopNetwork,TopNetworkModule}
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trait PeripherySPI {
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this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
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val spiDevices = (spiConfigs.zipWithIndex) map {case (c, i) =>
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val spi = LazyModule(new TLSPI(c) { override lazy val valName = Some(s"spi$i") } )
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spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := spi.intnode
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spi
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}
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}
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trait PeripherySPIBundle {
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this: { val spiConfigs: Seq[SPIConfig] } =>
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val spi_bc = spiConfigs.map(_.bc).reduce(_.union(_))
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val spis = Vec(spiConfigs.size, new SPIPortIO(spi_bc.toSPIConfig))
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}
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trait PeripherySPIModule {
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this: TopNetworkModule {
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val spiConfigs: Seq[SPIConfig]
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val outer: PeripherySPI
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val io: PeripherySPIBundle
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} =>
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(io.spis zip outer.spiDevices).foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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trait PeripherySPIFlash {
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this: TopNetwork { val spiFlashConfig: SPIFlashConfig } =>
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val qspi = LazyModule(new TLSPIFlash(spiFlashConfig))
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qspi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusConfig.beatBytes)(peripheryBus.node))
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intBus.intnode := qspi.intnode
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}
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trait PeripherySPIFlashBundle {
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this: { val spiFlashConfig: SPIFlashConfig } =>
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val qspi = new SPIPortIO(spiFlashConfig)
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}
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trait PeripherySPIFlashModule {
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this: TopNetworkModule {
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val spiConfigs: Seq[SPIConfig]
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val outer: PeripherySPIFlash
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val io: PeripherySPIFlashBundle
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} =>
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io.qspi <> outer.qspi.module.io.port
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}
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