122 lines
3.1 KiB
Scala
122 lines
3.1 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.spi
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import Chisel._
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class SPILinkIO(c: SPIConfigBase) extends SPIBundle(c) {
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val tx = Decoupled(Bits(width = c.frameBits))
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val rx = Valid(Bits(width = c.frameBits)).flip
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val cnt = UInt(OUTPUT, c.countBits)
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val fmt = new SPIFormat(c).asOutput
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val cs = new Bundle {
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val set = Bool(OUTPUT)
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val clear = Bool(OUTPUT) // Deactivate CS
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val hold = Bool(OUTPUT) // Supress automatic CS deactivation
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}
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val active = Bool(INPUT)
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}
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class SPIMedia(c: SPIConfigBase) extends Module {
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val io = new Bundle {
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val port = new SPIPortIO(c)
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val ctrl = new Bundle {
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val sck = new SPIClocking(c).asInput
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val dla = new SPIDelay(c).asInput
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val cs = new SPIChipSelect(c).asInput
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}
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val link = new SPILinkIO(c).flip
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}
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val phy = Module(new SPIPhysical(c))
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phy.io.ctrl.sck := io.ctrl.sck
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phy.io.ctrl.fmt := io.link.fmt
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private val op = phy.io.op
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op.valid := Bool(true)
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op.bits.fn := SPIMicroOp.Delay
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op.bits.stb := Bool(false)
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op.bits.cnt := io.link.cnt
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op.bits.data := io.link.tx.bits
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val cs = Reg(io.ctrl.cs)
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val cs_set = Reg(Bool())
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val cs_active = io.ctrl.cs.toggle(io.link.cs.set)
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val cs_update = (cs_active.asUInt =/= cs.dflt.asUInt)
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val clear = Reg(init = Bool(false))
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val cs_assert = Reg(init = Bool(false))
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val cs_deassert = clear || (cs_update && !io.link.cs.hold)
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clear := clear || (io.link.cs.clear && cs_assert)
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val continuous = (io.ctrl.dla.interxfr === UInt(0))
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io.port.sck := phy.io.port.sck
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io.port.dq <> phy.io.port.dq
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io.port.cs := cs.dflt
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io.link.rx := phy.io.rx
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io.link.tx.ready := Bool(false)
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io.link.active := cs_assert
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val (s_main :: s_interxfr :: s_intercs :: Nil) = Enum(UInt(), 3)
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val state = Reg(init = s_main)
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switch (state) {
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is (s_main) {
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when (cs_assert) {
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when (cs_deassert) {
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op.bits.cnt := io.ctrl.dla.sckcs
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when (op.ready) {
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state := s_intercs
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}
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} .otherwise {
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op.bits.fn := SPIMicroOp.Transfer
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op.bits.stb := Bool(true)
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op.valid := io.link.tx.valid
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io.link.tx.ready := op.ready
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when (op.fire()) {
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state := s_interxfr
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}
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}
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} .elsewhen (io.link.tx.valid) {
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// Assert CS
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op.bits.cnt := io.ctrl.dla.cssck
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when (op.ready) {
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cs_assert := Bool(true)
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cs_set := io.link.cs.set
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cs.dflt := cs_active
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}
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} .otherwise {
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// Idle
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op.bits.cnt := UInt(0)
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op.bits.stb := Bool(true)
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cs := io.ctrl.cs
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}
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}
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is (s_interxfr) {
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// Skip if interxfr delay is zero
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op.valid := !continuous
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op.bits.cnt := io.ctrl.dla.interxfr
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when (op.ready || continuous) {
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state := s_main
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}
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}
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is (s_intercs) {
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// Deassert CS
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op.bits.cnt := io.ctrl.dla.intercs
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op.bits.stb := Bool(true)
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cs_assert := Bool(false)
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clear := Bool(false)
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when (op.ready) {
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cs.dflt := cs.toggle(cs_set)
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state := s_main
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}
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}
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}
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}
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