107 lines
2.7 KiB
Scala
107 lines
2.7 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.spi
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import Chisel._
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abstract class SPIBundle(val c: SPIConfigBase) extends Bundle {
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override def cloneType: SPIBundle.this.type =
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this.getClass.getConstructors.head.newInstance(c).asInstanceOf[this.type]
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}
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class SPIDataIO extends Bundle {
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val i = Bool(INPUT)
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val o = Bool(OUTPUT)
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val oe = Bool(OUTPUT)
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}
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class SPIPortIO(c: SPIConfigBase) extends SPIBundle(c) {
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val sck = Bool(OUTPUT)
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val dq = Vec(4, new SPIDataIO)
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val cs = Vec(c.csWidth, Bool(OUTPUT))
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}
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trait HasSPIProtocol {
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val proto = Bits(width = SPIProtocol.width)
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}
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trait HasSPIEndian {
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val endian = Bits(width = SPIEndian.width)
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}
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class SPIFormat(c: SPIConfigBase) extends SPIBundle(c)
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with HasSPIProtocol
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with HasSPIEndian {
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val iodir = Bits(width = SPIDirection.width)
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}
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trait HasSPILength extends SPIBundle {
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val len = UInt(width = c.lengthBits)
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}
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class SPIClocking(c: SPIConfigBase) extends SPIBundle(c) {
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val div = UInt(width = c.divisorBits)
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val pol = Bool()
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val pha = Bool()
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}
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class SPIChipSelect(c: SPIConfigBase) extends SPIBundle(c) {
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val id = UInt(width = c.csIdBits)
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val dflt = Vec(c.csWidth, Bool())
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def toggle(en: Bool): Vec[Bool] = {
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val mask = en << id
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val out = Cat(dflt.reverse) ^ mask
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Vec.tabulate(c.csWidth)(out(_))
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}
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}
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trait HasSPICSMode {
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val mode = Bits(width = SPICSMode.width)
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}
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class SPIDelay(c: SPIConfigBase) extends SPIBundle(c) {
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val cssck = UInt(width = c.delayBits)
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val sckcs = UInt(width = c.delayBits)
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val intercs = UInt(width = c.delayBits)
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val interxfr = UInt(width = c.delayBits)
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}
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class SPIWatermark(c: SPIConfigBase) extends SPIBundle(c) {
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val tx = UInt(width = c.txDepthBits)
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val rx = UInt(width = c.rxDepthBits)
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}
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class SPIControl(c: SPIConfigBase) extends SPIBundle(c) {
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val fmt = new SPIFormat(c) with HasSPILength
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val sck = new SPIClocking(c)
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val cs = new SPIChipSelect(c) with HasSPICSMode
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val dla = new SPIDelay(c)
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val wm = new SPIWatermark(c)
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}
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object SPIControl {
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def init(c: SPIConfigBase): SPIControl = {
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val ctrl = Wire(new SPIControl(c))
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ctrl.fmt.proto := SPIProtocol.Single
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ctrl.fmt.iodir := SPIDirection.Rx
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ctrl.fmt.endian := SPIEndian.MSB
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ctrl.fmt.len := UInt(math.min(c.frameBits, 8))
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ctrl.sck.div := UInt(3)
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ctrl.sck.pol := Bool(false)
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ctrl.sck.pha := Bool(false)
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ctrl.cs.id := UInt(0)
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ctrl.cs.dflt.foreach { _ := Bool(true) }
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ctrl.cs.mode := SPICSMode.Auto
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ctrl.dla.cssck := UInt(1)
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ctrl.dla.sckcs := UInt(1)
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ctrl.dla.intercs := UInt(1)
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ctrl.dla.interxfr := UInt(0)
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ctrl.wm.tx := UInt(0)
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ctrl.wm.rx := UInt(0)
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ctrl
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}
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}
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class SPIInterrupts extends Bundle {
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val txwm = Bool()
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val rxwm = Bool()
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}
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