41 lines
1.1 KiB
Scala
41 lines
1.1 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.spi
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import Chisel._
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class SPIInnerIO(c: SPIConfigBase) extends SPILinkIO(c) {
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val lock = Bool(OUTPUT)
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}
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class SPIArbiter(c: SPIConfigBase, n: Int) extends Module {
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val io = new Bundle {
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val inner = Vec(n, new SPIInnerIO(c)).flip
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val outer = new SPILinkIO(c)
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val sel = UInt(INPUT, log2Up(n))
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}
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val sel = Reg(init = Vec(Bool(true) +: Seq.fill(n-1)(Bool(false))))
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io.outer.tx.valid := Mux1H(sel, io.inner.map(_.tx.valid))
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io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits))
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io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt))
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io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt))
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io.outer.cs := Mux1H(sel, io.inner.map(_.cs))
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(io.inner zip sel).foreach { case (inner, s) =>
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inner.tx.ready := io.outer.tx.ready && s
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inner.rx.valid := io.outer.rx.valid && s
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inner.rx.bits := io.outer.rx.bits
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inner.active := io.outer.active && s
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}
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val nsel = Vec.tabulate(n)(io.sel === UInt(_))
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val lock = Mux1H(sel, io.inner.map(_.lock))
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when (!lock) {
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sel := nsel
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when (sel.asUInt =/= nsel.asUInt) {
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io.outer.cs.clear := Bool(true)
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}
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}
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}
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