59 lines
1.6 KiB
Scala
59 lines
1.6 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.pwm
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import Chisel._
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import config._
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import diplomacy.LazyModule
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import rocketchip.{TopNetwork,TopNetworkModule}
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import uncore.tilelink2.TLFragmenter
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import sifive.blocks.devices.gpio._
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class PWMPortIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
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val port = Vec(c.ncmp, Bool()).asOutput
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override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
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}
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class PWMPinsIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
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val pwm = Vec(c.ncmp, new GPIOPin)
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}
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class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val pwm = new PWMPortIO(c).flip()
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val pins = new PWMPinsIO(c)
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}
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GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
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}
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trait PeripheryPWM {
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this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
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val pwmDevices = (pwmConfigs.zipWithIndex) map { case (c, i) =>
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val pwm = LazyModule(new TLPWM(c) { override lazy val valName = Some(s"pwm$i") })
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pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := pwm.intnode
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pwm
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}
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}
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trait PeripheryPWMBundle {
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this: {
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val p: Parameters
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val pwmConfigs: Seq[PWMConfig]
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} =>
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val pwm_bc = pwmConfigs.map(_.bc).reduce(_.union(_))
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val pwms = Vec(pwmConfigs.size, new PWMPortIO(pwm_bc)(p))
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}
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trait PeripheryPWMModule {
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this: TopNetworkModule {
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val outer: PeripheryPWM
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val io: PeripheryPWMBundle
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} =>
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(io.pwms.zipWithIndex zip outer.pwmDevices) foreach { case ((io, i), device) =>
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io.port := device.module.io.gpio
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}
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}
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