83 lines
3.0 KiB
Scala
83 lines
3.0 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.pwm
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import Chisel._
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import Chisel.ImplicitConversions._
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import config._
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import regmapper._
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import rocketchip.PeripheryBusConfig
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import uncore.tilelink2._
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import util._
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import sifive.blocks.util.GenericTimer
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// Core PWM Functionality & Register Interface
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class PWM(val ncmp: Int = 4, val cmpWidth: Int = 16)(implicit p: Parameters) extends GenericTimer {
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protected def countWidth = ((1 << scaleWidth) - 1) + cmpWidth
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protected lazy val countAlways = RegEnable(io.regs.cfg.write.bits(12), Bool(false), io.regs.cfg.write.valid && unlocked)
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protected lazy val feed = count.carryOut(scale + UInt(cmpWidth))
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protected lazy val countEn = Wire(Bool())
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override protected lazy val oneShot = RegEnable(io.regs.cfg.write.bits(13) && !countReset, Bool(false), (io.regs.cfg.write.valid && unlocked) || countReset)
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override protected lazy val center = RegEnable(io.regs.cfg.write.bits(16 + ncmp - 1, 16), io.regs.cfg.write.valid && unlocked)
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override protected lazy val gang = RegEnable(io.regs.cfg.write.bits(24 + ncmp - 1, 24), io.regs.cfg.write.valid && unlocked)
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override protected lazy val deglitch = RegEnable(io.regs.cfg.write.bits(10), io.regs.cfg.write.valid && unlocked)(0)
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override protected lazy val sticky = RegEnable(io.regs.cfg.write.bits(8), io.regs.cfg.write.valid && unlocked)(0)
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override protected lazy val ip = {
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val doSticky = Reg(next = (deglitch && !countReset) || sticky)
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val sel = ((0 until ncmp).map(i => s(cmpWidth-1) && center(i))).asUInt
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val reg = Reg(UInt(width = ncmp))
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reg := (sel & elapsed.asUInt) | (~sel & (elapsed.asUInt | (Fill(ncmp, doSticky) & reg)))
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when (io.regs.cfg.write.valid && unlocked) { reg := io.regs.cfg.write.bits(28 + ncmp - 1, 28) }
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reg
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}
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lazy val io = new GenericTimerIO {
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val gpio = Vec(ncmp, Bool()).asOutput
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}
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io.gpio := io.gpio.fromBits(ip & ~(gang & Cat(ip(0), ip >> 1)))
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countEn := countAlways || oneShot
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}
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case class PWMConfig(
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address: BigInt,
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size: Int = 0x1000,
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regBytes: Int = 4,
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ncmp: Int = 4,
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cmpWidth: Int = 16)
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{
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val bc = new PWMBundleConfig(ncmp)
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}
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case class PWMBundleConfig(
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ncmp: Int)
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{
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def union(that: PWMBundleConfig): PWMBundleConfig =
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PWMBundleConfig(scala.math.max(ncmp, that.ncmp))
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}
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trait HasPWMParameters {
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val params: (PWMConfig, Parameters)
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val c = params._1
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implicit val p = params._2
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}
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trait PWMBundle extends Bundle with HasPWMParameters {
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val gpio = Vec(c.ncmp, Bool()).asOutput
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}
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trait PWMModule extends Module with HasRegMap with HasPWMParameters {
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val io: PWMBundle
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val pwm = Module(new PWM(c.ncmp, c.cmpWidth))
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interrupts := pwm.io.ip
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io.gpio := pwm.io.gpio
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regmap((GenericTimer.timerRegMap(pwm, 0, c.regBytes)):_*)
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}
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class TLPWM(c: PWMConfig)(implicit val p: Parameters)
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extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes)(
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new TLRegBundle((c, p), _) with PWMBundle)(
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new TLRegModule((c, p), _, _) with PWMModule)
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