43 lines
1.2 KiB
Scala
43 lines
1.2 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.mockaon
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import Chisel._
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import diplomacy.LazyModule
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import rocketchip.{TopNetwork,TopNetworkModule}
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import uncore.tilelink2.{IntXing, TLAsyncCrossingSource, TLFragmenter}
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import coreplex._
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trait PeripheryMockAON extends TopNetwork {
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val mockAONConfig: MockAONConfig
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val coreplex: CoreplexRISCVPlatform
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// We override the clock & Reset here so that all synchronizers, etc
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// are in the proper clock domain.
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val aon = LazyModule(new MockAONWrapper(mockAONConfig))
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val aon_int = LazyModule(new IntXing)
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aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node))
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aon_int.intnode := aon.intnode
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intBus.intnode := aon_int.intnode
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}
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trait PeripheryMockAONBundle {
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val aon = new MockAONWrapperBundle()
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}
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trait PeripheryMockAONModule {
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this: TopNetworkModule {
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val outer: PeripheryMockAON
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val io: PeripheryMockAONBundle
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} =>
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io.aon <> outer.aon.module.io
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// Explicit clock & reset are unused in MockAONWrapper.
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// Tie to check this assumption.
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outer.aon.module.clock := Bool(false).asClock
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outer.aon.module.reset := Bool(true)
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outer.coreplex.module.io.rtcToggle := outer.aon.module.io.rtc.asUInt.toBool
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}
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