106 lines
3.0 KiB
Scala
106 lines
3.0 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.mockaon
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import Chisel._
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import config._
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import regmapper._
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import uncore.tilelink2._
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import rocketchip.PeripheryBusConfig
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import sifive.blocks.util.GenericTimer
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case class MockAONConfig(
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address: BigInt = BigInt(0x10000000),
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nBackupRegs: Int = 16) {
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def size: Int = 0x1000
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def regBytes: Int = 4
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def wdogOffset: Int = 0
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def rtcOffset: Int = 0x40
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def backupRegOffset: Int = 0x80
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def pmuOffset: Int = 0x100
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}
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trait HasMockAONParameters {
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val params: (MockAONConfig, Parameters)
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val c = params._1
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implicit val p = params._2
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}
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class MockAONPMUIO extends Bundle {
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val vddpaden = Bool(OUTPUT)
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val dwakeup = Bool(INPUT)
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}
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class MockAONMOffRstIO extends Bundle {
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val hfclkrst = Bool(OUTPUT)
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val corerst = Bool(OUTPUT)
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}
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trait MockAONBundle extends Bundle with HasMockAONParameters {
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// Output of the Power Management Sequencer
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val moff = new MockAONMOffRstIO ()
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// This goes out to wrapper
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// to be combined to create aon_rst.
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val wdog_rst = Bool(OUTPUT)
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// This goes out to wrapper
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// and comes back as our clk
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val lfclk = Clock(OUTPUT)
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val pmu = new MockAONPMUIO
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val lfextclk = Clock(INPUT)
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val resetCauses = new ResetCauses().asInput
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}
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trait MockAONModule extends Module with HasRegMap with HasMockAONParameters {
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val io: MockAONBundle
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// the expectation here is that Chisel's implicit reset is aonrst,
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// which is asynchronous, so don't use synchronous-reset registers.
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val rtc = Module(new RTC)
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val pmu = Module(new PMU(new DevKitPMUConfig))
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io.moff <> pmu.io.control
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io.pmu.vddpaden := pmu.io.control.vddpaden
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pmu.io.wakeup.dwakeup := io.pmu.dwakeup
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pmu.io.wakeup.awakeup := Bool(false)
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pmu.io.wakeup.rtc := rtc.io.ip(0)
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pmu.io.resetCauses := io.resetCauses
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val pmuRegMap = {
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val regs = pmu.io.regs.wakeupProgram ++ pmu.io.regs.sleepProgram ++
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Seq(pmu.io.regs.ie, pmu.io.regs.cause, pmu.io.regs.sleep, pmu.io.regs.key)
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for ((r, i) <- regs.zipWithIndex)
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yield (c.pmuOffset + c.regBytes*i) -> Seq(r.toRegField())
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}
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interrupts(1) := rtc.io.ip(0)
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val wdog = Module(new WatchdogTimer)
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io.wdog_rst := wdog.io.rst
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wdog.io.corerst := pmu.io.control.corerst
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interrupts(0) := wdog.io.ip(0)
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// If there are multiple lfclks to choose from, we can mux them here.
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io.lfclk := io.lfextclk
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val backupRegs = Seq.fill(c.nBackupRegs)(Reg(UInt(width = c.regBytes * 8)))
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val backupRegMap =
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for ((reg, i) <- backupRegs.zipWithIndex)
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yield (c.backupRegOffset + c.regBytes*i) -> Seq(RegField(reg.getWidth, RegReadFn(reg), RegWriteFn(reg)))
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regmap((backupRegMap ++
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GenericTimer.timerRegMap(wdog, c.wdogOffset, c.regBytes) ++
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GenericTimer.timerRegMap(rtc, c.rtcOffset, c.regBytes) ++
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pmuRegMap):_*)
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}
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class MockAON(c: MockAONConfig)(implicit val p: Parameters)
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extends TLRegisterRouter(c.address, interrupts = 2, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes, concurrency = 1)(
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new TLRegBundle((c, p), _) with MockAONBundle)(
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new TLRegModule((c, p), _, _) with MockAONModule)
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