62 lines
1.8 KiB
Scala
62 lines
1.8 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.uart
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import Chisel._
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import freechips.rocketchip.config.Field
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import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
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import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
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import sifive.blocks.util.ShiftRegisterInit
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case object PeripheryUARTKey extends Field[Seq[UARTParams]]
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trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
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val uartParams = p(PeripheryUARTKey)
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val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
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val uarts = uartParams map { params =>
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val uart = LazyModule(new TLUART(pbus.beatBytes, params.copy(divisorInit = divinit)))
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uart.node := pbus.toVariableWidthSlaves
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ibus.fromSync := uart.intnode
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uart
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}
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}
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trait HasPeripheryUARTBundle {
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val uarts: Vec[UARTPortIO]
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def tieoffUARTs(dummy: Int = 1) {
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uarts.foreach { _.rxd := UInt(1) }
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}
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def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
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val pins = Module(new UARTGPIOPort(syncStages))
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pins.io.uart <> u
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pins.io.pins
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}
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}
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trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
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val outer: HasPeripheryUART
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val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
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(uarts zip outer.uarts).foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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class UARTPinsIO extends Bundle {
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val rxd = new GPIOPin
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val txd = new GPIOPin
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}
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class UARTGPIOPort(syncStages: Int = 0) extends Module {
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val io = new Bundle{
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val uart = new UARTPortIO().flip()
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val pins = new UARTPinsIO
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}
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GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
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val rxd = GPIOInputPinCtrl(io.pins.rxd)
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io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))
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}
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