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@ -10,7 +10,7 @@ import freechips.rocketchip.regmapper._
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import freechips.rocketchip.subsystem.{BaseSubsystem}
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import freechips.rocketchip.subsystem.{BaseSubsystem}
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util.AsyncQueue
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import freechips.rocketchip.util.AsyncQueue
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import sifive.blocks.util.NonBlockingEnqueue
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case class TerminalParams (
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case class TerminalParams (
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address: BigInt
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address: BigInt
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@ -69,18 +69,8 @@ trait TerminalRegModule extends MultiIOModule with HasRegMap {
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term.io.write_data := crossing.io.deq.bits
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term.io.write_data := crossing.io.deq.bits
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crossing.io.deq.ready := Bool(true) // terminal can read at every cycle
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crossing.io.deq.ready := Bool(true) // terminal can read at every cycle
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val writer_fn = (valid: Bool, data: UInt) => {
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crossing.io.enq.valid := valid
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crossing.io.enq.bits := data
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Bool(true) // discards values if queue is full (see NonBlockingEnqueue)
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}
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regmap(
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regmap(
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0 -> Seq (
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0 -> NonBlockingEnqueue(crossing.io.enq)
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RegField.w(8, writer_fn, RegFieldDesc(
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"write", "Write an ASCII character to the terminal."
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))
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)
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)
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)
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}
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}
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