116 lines
3.3 KiB
Scala
116 lines
3.3 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.terminal
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import Chisel._
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import chisel3.core.{Input, Output}
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import chisel3.experimental.{Analog, MultiIOModule}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.subsystem.{BaseSubsystem}
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util.AsyncQueue
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import sifive.blocks.util.NonBlockingEnqueue
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case class TerminalParams (
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address: BigInt
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)
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class TerminalSysIO extends Bundle {
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val clk = Input(Clock())
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val reset = Input(Bool())
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}
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class TerminalDVIIO extends Bundle {
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val d = Output(Bits(12.W))
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val clk_p = Output(Bits(1.W))
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val clk_n = Output(Bits(1.W))
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val hsync = Output(Bool())
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val vsync = Output(Bool())
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val de = Output(Bool())
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val reset = Output(Bool())
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val i2c_scl = Analog(1.W)
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val i2c_sda = Analog(1.W)
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}
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class Terminal extends BlackBox {
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val io = IO(new Bundle {
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val sys = new TerminalSysIO
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val dvi = new TerminalDVIIO
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val write_enable = Input(Bool())
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val write_data = Input(UInt(8.W))
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})
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override def desiredName: String = "terminal"
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}
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trait TerminalRegBundle extends Bundle {
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val port_sys = new TerminalSysIO
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val port_dvi = new TerminalDVIIO
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}
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trait TerminalRegModule extends MultiIOModule with HasRegMap {
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val params: TerminalParams
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val io: TerminalRegBundle
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val term = Module(new Terminal)
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io.port_sys <> term.io.sys
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io.port_dvi <> term.io.dvi
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val crossing = Module(new AsyncQueue(UInt(8.W), depth=1, safe=false))
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crossing.io.enq_clock := clock
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crossing.io.enq_reset := Bool(false)
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crossing.io.deq_clock := io.port_sys.clk
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crossing.io.deq_reset := Bool(false)
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// wire up dequeue to terminal io
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term.io.write_enable := crossing.io.deq.valid
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term.io.write_data := crossing.io.deq.bits
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crossing.io.deq.ready := Bool(true) // terminal can read at every cycle
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regmap(
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0 -> NonBlockingEnqueue(crossing.io.enq)
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)
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}
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class TLTerminal(w: Int, params: TerminalParams)(implicit p: Parameters)
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extends TLRegisterRouter (
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params.address,
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"terminal",
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Seq("klemens,terminal0"),
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beatBytes = w
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)(
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new TLRegBundle(params, _) with TerminalRegBundle
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)(
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new TLRegModule(params, _, _) with TerminalRegModule
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)
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//-- TerminalPeriphery
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case object PeripheryTerminalKey extends Field[TerminalParams]
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trait HasPeripheryTerminal { this: BaseSubsystem =>
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val params = p(PeripheryTerminalKey)
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val terminal_name = Some("terminal_0")
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val terminal = LazyModule(new TLTerminal(pbus.beatBytes, params))
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.suggestName(terminal_name)
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pbus.toVariableWidthSlave(terminal_name) { terminal.node }
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}
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trait HasPeripheryTerminalBundle {
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val terminal: TerminalSysIO
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val dvi: TerminalDVIIO
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}
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trait HasPeripheryTerminalModuleImp extends LazyModuleImp with HasPeripheryTerminalBundle {
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val outer: HasPeripheryTerminal
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val terminal = IO(new TerminalSysIO)
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val dvi = IO(new TerminalDVIIO)
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// right sides defined in TerminalRegBundle
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terminal <> outer.terminal.module.io.port_sys
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dvi <> outer.terminal.module.io.port_dvi
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}
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