riscv/sifive-blocks
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Author SHA1 Message Date
Wesley W. Terpstra
45c491cd69 LazyModule: provide Parameters 
This tracks PR #478 in rocketchip.
 2016-12-07 13:21:20 -08:00
Wesley W. Terpstra
1443834186 xilinx pcie: bytes, not bits 
This bug amazingly compiled correctly and ran correctly!

It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.

The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
 2016-12-06 16:13:12 -08:00
SiFive
7916ef5249 Initial commit. 2016-11-29 04:08:44 -08:00