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Refactor package hierarchy. (#25)

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This commit is contained in:
Henry Cook
2017-07-07 10:48:57 -07:00
committed by GitHub
parent 66b2fd11bd
commit fb9dd31374
27 changed files with 100 additions and 99 deletions
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8
src/main/scala/devices/gpio/GPIO.scala
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@@ -2,10 +2,10 @@
package sifive.blocks.devices.gpio
import Chisel._
import config.Parameters
import regmapper._
import uncore.tilelink2._
import util.{AsyncResetRegVec, GenericParameterizedBundle}
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)

10
src/main/scala/devices/gpio/GPIOPeriphery.scala
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@@ -2,11 +2,11 @@
package sifive.blocks.devices.gpio
import Chisel._
import config.Field
import diplomacy.{LazyModule,LazyMultiIOModuleImp}
import rocketchip.HasSystemNetworks
import uncore.tilelink2.TLFragmenter
import util.HeterogeneousBag
import freechips.rocketchip.config.Field
import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
import freechips.rocketchip.tilelink.TLFragmenter
import freechips.rocketchip.util.HeterogeneousBag
case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]

4
src/main/scala/devices/gpio/JTAG.scala
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@@ -10,8 +10,8 @@ import Chisel._
// to put them otherwise.
// ------------------------------------------------------------
import config._
import jtag.{JTAGIO}
import freechips.rocketchip.config._
import freechips.rocketchip.jtag.{JTAGIO}
class JTAGPinsIO(hasTRSTn: Boolean = true) extends Bundle {

8
src/main/scala/devices/i2c/I2C.scala
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@@ -42,10 +42,10 @@
package sifive.blocks.devices.i2c
import Chisel._
import config._
import regmapper._
import uncore.tilelink2._
import util.{AsyncResetRegVec, Majority}
import freechips.rocketchip.config._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{AsyncResetRegVec, Majority}
import sifive.blocks.devices.gpio.{GPIOPinCtrl}
case class I2CParams(address: BigInt)

8
src/main/scala/devices/i2c/I2CPeriphery.scala
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@@ -2,10 +2,10 @@
package sifive.blocks.devices.i2c
import Chisel._
import config.Field
import diplomacy.{LazyModule,LazyMultiIOModuleImp}
import rocketchip.{HasSystemNetworks}
import uncore.tilelink2.TLFragmenter
import freechips.rocketchip.config.Field
import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
import freechips.rocketchip.chip.{HasSystemNetworks}
import freechips.rocketchip.tilelink.TLFragmenter
case object PeripheryI2CKey extends Field[Seq[I2CParams]]

6
src/main/scala/devices/mockaon/MockAON.scala
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@@ -2,9 +2,9 @@
package sifive.blocks.devices.mockaon
import Chisel._
import config._
import regmapper._
import uncore.tilelink2._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import sifive.blocks.util.GenericTimer

10
src/main/scala/devices/mockaon/MockAONPeriphery.scala
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@@ -2,11 +2,11 @@
package sifive.blocks.devices.mockaon
import Chisel._
import config.Field
import diplomacy.{LazyModule, LazyMultiIOModuleImp}
import rocketchip.{HasSystemNetworks, HasCoreplexRISCVPlatform}
import uncore.tilelink2.{IntXing, TLAsyncCrossingSource, TLFragmenter}
import util.ResetCatchAndSync
import freechips.rocketchip.config.Field
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.{HasSystemNetworks, HasCoreplexRISCVPlatform}
import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource, TLFragmenter}
import freechips.rocketchip.util.ResetCatchAndSync
case object PeripheryMockAONKey extends Field[MockAONParams]

9
src/main/scala/devices/mockaon/MockAONWrapper.scala
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@@ -2,12 +2,13 @@
package sifive.blocks.devices.mockaon
import Chisel._
import config._
import diplomacy._
import uncore.tilelink2._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
import sifive.blocks.util.{DeglitchShiftRegister, ResetCatchAndSync}
import util._
/* The wrapper handles the Clock and Reset Generation for The AON block itself,
and instantiates real pad controls (aka pull-ups)*/

2
src/main/scala/devices/mockaon/PMU.scala
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@@ -3,7 +3,7 @@ package sifive.blocks.devices.mockaon
import Chisel._
import Chisel.ImplicitConversions._
import util._
import freechips.rocketchip.util._
import sifive.blocks.util.SRLatch
import sifive.blocks.util.{SlaveRegIF}

2
src/main/scala/devices/mockaon/WatchdogTimer.scala
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@@ -3,7 +3,7 @@ package sifive.blocks.devices.mockaon
import Chisel._
import Chisel.ImplicitConversions._
import util.AsyncResetReg
import freechips.rocketchip.util.AsyncResetReg
import sifive.blocks.util.{SlaveRegIF, GenericTimer}

9
src/main/scala/devices/pwm/PWM.scala
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@@ -3,11 +3,10 @@ package sifive.blocks.devices.pwm
import Chisel._
import Chisel.ImplicitConversions._
import config.Parameters
import regmapper._
import uncore.tilelink2._
import util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import sifive.blocks.util.GenericTimer
// Core PWM Functionality & Register Interface

10
src/main/scala/devices/pwm/PWMPeriphery.scala
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@@ -2,11 +2,11 @@
package sifive.blocks.devices.pwm
import Chisel._
import config.Field
import diplomacy.{LazyModule,LazyMultiIOModuleImp}
import rocketchip.HasSystemNetworks
import uncore.tilelink2.TLFragmenter
import util.HeterogeneousBag
import freechips.rocketchip.config.Field
import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
import freechips.rocketchip.tilelink.TLFragmenter
import freechips.rocketchip.util.HeterogeneousBag
import sifive.blocks.devices.gpio._

2
src/main/scala/devices/spi/SPIBundle.scala
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@@ -2,7 +2,7 @@
package sifive.blocks.devices.spi
import Chisel._
import util.GenericParameterizedBundle
import freechips.rocketchip.util.GenericParameterizedBundle
abstract class SPIBundle(val c: SPIParamsBase) extends GenericParameterizedBundle(c) {
override def cloneType: SPIBundle.this.type =

10
src/main/scala/devices/spi/SPIPeriphery.scala
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@@ -2,11 +2,11 @@
package sifive.blocks.devices.spi
import Chisel._
import config.Field
import diplomacy.{LazyModule,LazyMultiIOModuleImp}
import rocketchip.HasSystemNetworks
import uncore.tilelink2.{TLFragmenter,TLWidthWidget}
import util.HeterogeneousBag
import freechips.rocketchip.config.Field
import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]

12
src/main/scala/devices/spi/TLSPI.scala
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@@ -2,11 +2,11 @@
package sifive.blocks.devices.spi
import Chisel._
import config._
import diplomacy._
import regmapper._
import uncore.tilelink2._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.HeterogeneousBag
import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
trait SPIParamsBase {
@@ -47,7 +47,7 @@ case class SPIParams(
require(sampleDelay >= 0)
}
class SPITopBundle(val i: util.HeterogeneousBag[Vec[Bool]], val r: util.HeterogeneousBag[TLBundle]) extends Bundle
class SPITopBundle(val i: HeterogeneousBag[Vec[Bool]], val r: HeterogeneousBag[TLBundle]) extends Bundle
class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLSPIBase)
extends LazyModuleImp(outer) {

11
src/main/scala/devices/spi/TLSPIFlash.scala
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@@ -2,10 +2,11 @@
package sifive.blocks.devices.spi
import Chisel._
import config._
import diplomacy._
import regmapper._
import uncore.tilelink2._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.HeterogeneousBag
trait SPIFlashParamsBase extends SPIParamsBase {
val fAddress: BigInt
@@ -38,7 +39,7 @@ case class SPIFlashParams(
require(sampleDelay >= 0)
}
class SPIFlashTopBundle(i: util.HeterogeneousBag[Vec[Bool]], r: util.HeterogeneousBag[TLBundle], val f: util.HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
class SPIFlashTopBundle(i: HeterogeneousBag[Vec[Bool]], r: HeterogeneousBag[TLBundle], val f: HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
class SPIFlashTopModule[B <: SPIFlashTopBundle]
(c: SPIFlashParamsBase, bundle: => B, outer: TLSPIFlashBase)

12
src/main/scala/devices/uart/UART.scala
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@@ -2,10 +2,12 @@
package sifive.blocks.devices.uart
import Chisel._
import config._
import regmapper._
import uncore.tilelink2._
import util._
import freechips.rocketchip.chip.RTCPeriod
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy.DTSTimebase
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
@@ -203,7 +205,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
val rxm = Module(new UARTRx(params))
val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
val divinit = p(diplomacy.DTSTimebase) * p(rocketchip.RTCPeriod) / 115200
val divinit = p(DTSTimebase) * p(RTCPeriod) / 115200
val div = Reg(init = UInt(divinit, uartDivisorBits))
private val stopCountBits = log2Up(uartStopBits)

9
src/main/scala/devices/uart/UARTPeriphery.scala
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@@ -2,11 +2,10 @@
package sifive.blocks.devices.uart
import Chisel._
import config.Field
import diplomacy.{LazyModule, LazyMultiIOModuleImp}
import rocketchip.HasSystemNetworks
import uncore.tilelink2.TLFragmenter
import freechips.rocketchip.config.Field
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
import freechips.rocketchip.tilelink.TLFragmenter
import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
import sifive.blocks.util.ShiftRegisterInit

13
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
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@@ -3,11 +3,12 @@ package sifive.blocks.devices.xilinxvc707mig
import Chisel._
import chisel3.experimental.{Analog,attach}
import config._
import diplomacy._
import uncore.tilelink2._
import uncore.axi4._
import rocketchip._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.chip._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
trait HasXilinxVC707MIGParameters {
@@ -34,7 +35,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
val xing = LazyModule(new TLAsyncCrossing)
val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
val deint = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes)))
val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
val yank = LazyModule(new AXI4UserYanker)
val buffer = LazyModule(new AXI4Buffer)

4
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
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@@ -2,8 +2,8 @@
package sifive.blocks.devices.xilinxvc707mig
import Chisel._
import diplomacy.{LazyModule, LazyMultiIOModuleImp}
import rocketchip.HasSystemNetworks
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
trait HasPeripheryXilinxVC707MIG extends HasSystemNetworks {
val module: HasPeripheryXilinxVC707MIGModuleImp

14
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@@ -2,11 +2,11 @@
package sifive.blocks.devices.xilinxvc707pciex1
import Chisel._
import config._
import diplomacy._
import uncore.tilelink2._
import uncore.axi4._
import rocketchip._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
import sifive.blocks.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
@@ -30,7 +30,7 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
axi_to_pcie_x1.slave :=
AXI4Buffer()(
AXI4UserYanker()(
AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
AXI4Deinterleaver(p(CacheBlockBytes))(
AXI4IdIndexer(idBits=4)(
TLToAXI4(beatBytes=8, adapterName = Some("pcie-slave"))(
TLAsyncCrossingSink()(
@@ -40,7 +40,7 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
AXI4Buffer()(
AXI4UserYanker(capMaxFlight = Some(2))(
TLToAXI4(beatBytes=4)(
TLFragmenter(4, p(coreplex.CacheBlockBytes))(
TLFragmenter(4, p(CacheBlockBytes))(
TLAsyncCrossingSink()(
control)))))

6
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
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@@ -2,9 +2,9 @@
package sifive.blocks.devices.xilinxvc707pciex1
import Chisel._
import diplomacy.{LazyModule, LazyMultiIOModuleImp}
import rocketchip.HasSystemNetworks
import uncore.tilelink2._
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
import freechips.rocketchip.tilelink._
trait HasPeripheryXilinxVC707PCIeX1 extends HasSystemNetworks {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)