61 lines
1.7 KiB
Scala
61 lines
1.7 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.pwm
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import Chisel._
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import freechips.rocketchip.config.Field
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import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
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import freechips.rocketchip.chip.HasSystemNetworks
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import freechips.rocketchip.tilelink.TLFragmenter
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import freechips.rocketchip.util.HeterogeneousBag
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import sifive.blocks.devices.gpio._
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class PWMPortIO(val c: PWMParams) extends Bundle {
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val port = Vec(c.ncmp, Bool()).asOutput
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override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
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}
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class PWMPinsIO(val c: PWMParams) extends Bundle {
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val pwm = Vec(c.ncmp, new GPIOPin)
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}
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class PWMGPIOPort(val c: PWMParams) extends Module {
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val io = new Bundle {
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val pwm = new PWMPortIO(c).flip()
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val pins = new PWMPinsIO(c)
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}
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GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
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}
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case object PeripheryPWMKey extends Field[Seq[PWMParams]]
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trait HasPeripheryPWM extends HasSystemNetworks {
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val pwmParams = p(PeripheryPWMKey)
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val pwms = pwmParams map { params =>
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val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
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pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := pwm.intnode
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pwm
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}
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}
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trait HasPeripheryPWMBundle {
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val pwms: HeterogeneousBag[PWMPortIO]
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def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMPinsIO] = pwms.map { p =>
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val pins = Module(new PWMGPIOPort(p.c))
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pins.io.pwm <> p
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pins.io.pins
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}
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}
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trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
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val outer: HasPeripheryPWM
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val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
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(pwms zip outer.pwms) foreach { case (io, device) =>
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io.port := device.module.io.gpio
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}
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}
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