riscv/sifive-blocks
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JTAG: make TRSTn optional for all helpers as well to match the IO.

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This commit is contained in:
Megan Wachs 2017-03-24 17:27:55 -07:00
parent 2c47cc4abd
commit faeb14dc5a
1 changed files with 6 additions and 6 deletions
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12
src/main/scala/devices/gpio/JTAG.scala
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@ -13,28 +13,28 @@ import Chisel._
import config._
import jtag.{JTAGIO}
class JTAGPinsIO extends Bundle {
class JTAGPinsIO(hasTRSTn: Boolean = true) extends Bundle {
val TCK = new GPIOPin()
val TMS = new GPIOPin()
val TDI = new GPIOPin()
val TDO = new GPIOPin()
val TRSTn = new GPIOPin()
val TRSTn = if (hasTRSTn) Option(new GPIOPin()) else None
}
class JTAGGPIOPort()(implicit p: Parameters) extends Module {
class JTAGGPIOPort(hasTRSTn: Boolean = true)(implicit p: Parameters) extends Module {
val io = new Bundle {
// TODO: make this not hard-coded true.
val jtag = new JTAGIO(hasTRSTn = true)
val pins = new JTAGPinsIO()
val jtag = new JTAGIO(hasTRSTn)
val pins = new JTAGPinsIO(hasTRSTn)
}
io.jtag.TCK := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
io.jtag.TMS := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
io.jtag.TDI := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
io.jtag.TRSTn.get := GPIOInputPinCtrl(io.pins.TRSTn, pue = Bool(true))
io.jtag.TRSTn.foreach{t => t := GPIOInputPinCtrl(io.pins.TRSTn.get, pue = Bool(true))}
GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO.data)
io.pins.TDO.o.oe := io.jtag.TDO.driven