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uart: use PeripheryBusKey (#38)

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Henry Cook 2017-09-15 14:54:10 -07:00 committed by GitHub
parent d5554bfe95
commit f8dcfbacfa
1 changed files with 2 additions and 2 deletions
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src/main/scala/devices/uart/UARTPeriphery.scala
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@ -5,14 +5,14 @@ import Chisel._
import chisel3.experimental.{withClockAndReset} import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field import freechips.rocketchip.config.Field
import freechips.rocketchip.util.SyncResetSynchronizerShiftReg import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus} import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin} import sifive.blocks.devices.pinctrl.{Pin}
case object PeripheryUARTKey extends Field[Seq[UARTParams]] case object PeripheryUARTKey extends Field[Seq[UARTParams]]
trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus { trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
private val divinit = (p(PeripheryBusParams).frequency / 115200).toInt private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit)) val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
val uarts = uartParams map { params => val uarts = uartParams map { params =>
val uart = LazyModule(new TLUART(pbus.beatBytes, params)) val uart = LazyModule(new TLUART(pbus.beatBytes, params))