From f8dcfbacfa2517ff195d06f03459c23c7c194634 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 15 Sep 2017 14:54:10 -0700 Subject: [PATCH] uart: use PeripheryBusKey (#38) --- src/main/scala/devices/uart/UARTPeriphery.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index f29716c..de4392c 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -5,14 +5,14 @@ import Chisel._ import chisel3.experimental.{withClockAndReset} import freechips.rocketchip.config.Field import freechips.rocketchip.util.SyncResetSynchronizerShiftReg -import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus} +import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import sifive.blocks.devices.pinctrl.{Pin} case object PeripheryUARTKey extends Field[Seq[UARTParams]] trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus { - private val divinit = (p(PeripheryBusParams).frequency / 115200).toInt + private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit)) val uarts = uartParams map { params => val uart = LazyModule(new TLUART(pbus.beatBytes, params))