riscv/sifive-blocks
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Remove pluralization on interface names. Require clocks and resets explicitly when necessary

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This commit is contained in:
Megan Wachs
2017-07-19 14:51:50 -07:00
parent 4d74e8f67f
commit ef4f2ed888
10 changed files with 74 additions and 49 deletions
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21
src/main/scala/devices/uart/UARTPeriphery.scala
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@ -2,6 +2,7 @@
package sifive.blocks.devices.uart
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
@ -22,31 +23,33 @@ trait HasPeripheryUART extends HasSystemNetworks {
}
trait HasPeripheryUARTBundle {
val uarts: Vec[UARTPortIO]
val uart: Vec[UARTPortIO]
def tieoffUARTs(dummy: Int = 1) {
uarts.foreach { _.rxd := UInt(1) }
uart.foreach { _.rxd := UInt(1) }
}
}
trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
val outer: HasPeripheryUART
val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
(uarts zip outer.uarts).foreach { case (io, device) =>
(uart zip outer.uarts).foreach { case (io, device) =>
io <> device.module.io.port
}
}
class UARTPins(pingen: () => Pin) extends Bundle {
class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
val rxd = pingen()
val txd = pingen()
def fromUARTPort(uart: UARTPortIO, syncStages: Int = 0) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
}
}
}