riscv/sifive-blocks
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Remove pluralization on interface names. Require clocks and resets explicitly when necessary

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This commit is contained in:
Megan Wachs
2017-07-19 14:51:50 -07:00
parent 4d74e8f67f
commit ef4f2ed888
10 changed files with 74 additions and 49 deletions
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10
src/main/scala/devices/gpio/GPIO.scala
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@ -34,6 +34,14 @@ object IOFCtrl {
// for the IOF
class IOFPin extends Pin {
val o = new IOFCtrl().asOutput
def default(): Unit = {
this.o.oval := Bool(false)
this.o.oe := Bool(false)
this.o.ie := Bool(false)
this.o.valid := Bool(false)
}
def inputPin(pue: Bool = Bool(false) /*ignored*/): Bool = {
this.o.oval := Bool(false)
this.o.oe := Bool(false)
@ -53,7 +61,7 @@ class IOFPin extends Pin {
// Connect both the i and o side of the pin,
// and drive the valid signal for the IOF.
object GPIOPinToIOF {
object BasePinToIOF {
def apply(pin: BasePin, iof: IOFPin): Unit = {
iof <> pin
iof.o.valid := Bool(true)