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sifive-blocks: update to new rocket API (#43)

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This commit is contained in:
Wesley W. Terpstra
2017-10-26 16:10:18 -07:00
committed by GitHub
parent e6da80733e
commit e4960a4e5a
3 changed files with 4 additions and 1 deletions
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3
src/main/scala/devices/mockaon/MockAONPeriphery.scala
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@@ -8,7 +8,8 @@ import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.devices.debug.HasPeripheryDebug
import freechips.rocketchip.devices.tilelink.HasPeripheryClint
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource}
import freechips.rocketchip.tilelink.{TLAsyncCrossingSource}
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util.ResetCatchAndSync
case object PeripheryMockAONKey extends Field[MockAONParams]

1
src/main/scala/devices/mockaon/MockAONWrapper.scala
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@@ -6,6 +6,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.interrupts._
import sifive.blocks.devices.pinctrl.{EnhancedPin}
import sifive.blocks.util.{DeglitchShiftRegister}

1
src/main/scala/devices/spi/TLSPI.scala
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@@ -6,6 +6,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util.HeterogeneousBag
import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}