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xilinx pcie: put buffers before the outputs to the controller

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This commit is contained in:
Wesley W. Terpstra 2017-01-20 22:38:27 -08:00
parent c68e44ec55
commit d61d86e084
1 changed files with 2 additions and 2 deletions
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src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@ -26,8 +26,8 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
val intnode = IntSourceNode(1)
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
axi_to_pcie_x1.slave := TLToAXI4(idBits=4)(slave)
axi_to_pcie_x1.control := AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control))
axi_to_pcie_x1.slave := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
lazy val module = new LazyModuleImp(this) {