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periphery: convert periphery bundle traits to work with system-level multi-io module

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This commit is contained in:
Henry Cook
2017-06-05 14:33:53 -07:00
parent 79f64de12c
commit d4bb8a77ea
8 changed files with 122 additions and 117 deletions
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34
src/main/scala/devices/uart/UARTPeriphery.scala
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@ -3,20 +3,16 @@ package sifive.blocks.devices.uart
import Chisel._
import config.Field
import diplomacy.LazyModule
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksBundle,
HasTopLevelNetworksModule
}
import uncore.tilelink2._
import diplomacy.{LazyModule, LazyMultiIOModuleImp}
import rocketchip.HasSystemNetworks
import uncore.tilelink2.TLFragmenter
import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
import sifive.blocks.util.ShiftRegisterInit
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
trait HasPeripheryUART extends HasTopLevelNetworks {
trait HasPeripheryUART extends HasSystemNetworks {
val uartParams = p(PeripheryUARTKey)
val uarts = uartParams map { params =>
val uart = LazyModule(new TLUART(peripheryBusBytes, params))
@ -26,15 +22,25 @@ trait HasPeripheryUART extends HasTopLevelNetworks {
}
}
trait HasPeripheryUARTBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripheryUART
val uarts = Vec(outer.uartParams.size, new UARTPortIO)
trait HasPeripheryUARTBundle {
val uarts: Vec[UARTPortIO]
def tieoffUARTs(dummy: Int = 1) {
uarts.foreach { _.rxd := UInt(1) }
}
def UARTtoGPIOPins(dummy: Int = 1): Seq[UARTGPIOPort] = uarts.map { u =>
val pin = Module(new UARTGPIOPort)
pin.io.uart <> u
pin
}
}
trait HasPeripheryUARTModule extends HasTopLevelNetworksModule {
trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
val outer: HasPeripheryUART
val io: HasPeripheryUARTBundle
(io.uarts zip outer.uarts).foreach { case (io, device) =>
val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
(uarts zip outer.uarts).foreach { case (io, device) =>
io <> device.module.io.port
}
}